Processor Datapath E85 Digital Design amp Computer Engineering Single Cycle Processor Datapath Lecture 19 Microarchitecture how to implement an architecture in hardware Processor Datapath ID: 1006632
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1. Lecture 19: Single CycleProcessor DatapathE85 Digital Design & Computer Engineering
2. Single Cycle Processor DatapathLecture 19
3. Microarchitecture: how to implement an architecture in hardwareProcessor:Datapath: functional blocksControl: control signalsIntroduction
4. Multiple implementations for a single architecture:Single-cycle: Each instruction executes in a single cycleMulticycle: Each instruction is broken up into series of shorter stepsPipelined: Each instruction broken up into series of steps & multiple instructions execute at onceMicroarchitecture
5. Program execution timeExecution Time = (#instructions)(cycles/instruction)(seconds/cycle)Definitions:CPI: Cycles/instructionclock period: seconds/cycleIPC: instructions/cycle = IPCChallenge is to satisfy constraints of:CostPowerPerformanceProcessor Performance
6. Consider subset of ARM instructions:Data-processing instructions: ADD, SUB, AND, ORRwith register and immediate Src2, but no shifts Memory instructions: LDR, STRwith positive immediate offsetBranch instructions: BARM Processor
7. Determines everything about a processor:Architectural state:16 registers (including PC)Status registerMemoryArchitectural State Elements
8. ARM Architectural State Elements
9. DatapathControlSingle-Cycle ARM Processor
10. DatapathControlSingle-Cycle ARM Processor
11. Datapath: start with LDR instructionExample: LDR R1, [R2, #5] LDR Rd, [Rn, imm12]Single-Cycle ARM Processor
12. STEP 1: Fetch instructionSingle-Cycle Datapath: LDR fetch
13. STEP 2: Read source operands from RFSingle-Cycle Datapath: LDR Reg ReadLDR Rd, [Rn, imm12]
14. STEP 3: Extend the immediateSingle-Cycle Datapath: LDR Immed.LDR Rd, [Rn, imm12]
15. STEP 4: Compute the memory addressSingle-Cycle Datapath: LDR AddressLDR Rd, [Rn, imm12]
16. LDR Rd, [Rn, imm12]STEP 5: Read data from memory and write it back to register fileSingle-Cycle Datapath: LDR Mem Read
17. STEP 6: Determine address of next instructionSingle-Cycle Datapath: PC Increment
18. PC can be source/destination of instructionSingle-Cycle Datapath: Access to PC
19. PC can be source/destination of instructionSource: R15 must be available in Register FilePC is read as the current PC plus 8Single-Cycle Datapath: Access to PC
20. PC can be source/destination of instructionSource: R15 must be available in Register FilePC is read as the current PC plus 8Destination: Be able to write result to PCSingle-Cycle Datapath: Access to PC
21. Expand datapath to handle STR:Write data in Rd to memorySingle-Cycle Datapath: STRSTR Rd, [Rn, imm12]
22. With immediate Src2:Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8 instead of Imm12)Write ALUResult to register fileWrite to RdSingle-Cycle Datapath: Data-processingADD Rd, Rn, imm8
23. With immediate Src2:Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8 instead of Imm12)Write ALUResult to register fileWrite to RdSingle-Cycle Datapath: Data-processingADD Rd, Rn, imm8
24. With register Src2:Read from Rn and Rm (instead of Imm8)Write ALUResult to register fileWrite to RdSingle-Cycle Datapath: Data-processingADD Rd, Rn, Rm
25. With register Src2:Read from Rn and Rm (instead of Imm8)Write ALUResult to register fileWrite to RdSingle-Cycle Datapath: Data-processingADD Rd, Rn, Rm
26. Calculate branch target address: BTA = (ExtImm) + (PC + 8) ExtImm = Imm24 << 2 and sign-extended Single-Cycle Datapath: BB Label
27. Single-Cycle Datapath: ExtImmImmSrc1:0ExtImmDescription00{24’b0, Instr7:0}Zero-extended imm801{20’b0, Instr11:0}Zero-extended imm1210{6{Instr23}, Instr23:0}Sign-extended imm24
28. Single-Cycle ARM Processor