/
–  1  – Data Converters	 Successive Approximation ADC	Professor Y. Chiu –  1  – Data Converters	 Successive Approximation ADC	Professor Y. Chiu

– 1 – Data Converters Successive Approximation ADC Professor Y. Chiu - PowerPoint Presentation

sherrill-nordquist
sherrill-nordquist . @sherrill-nordquist
Follow
347 views
Uploaded On 2018-09-22

– 1 – Data Converters Successive Approximation ADC Professor Y. Chiu - PPT Presentation

EECT 7327 Fall 2014 Successive Approximation SA ADC Successive Approximation ADC 2 Data Converters Successive Approximation ADC Professor Y Chiu EECT 7327 Fall 2014 Binary search algorithm N ID: 675038

successive adc data approximation adc successive approximation data 7327 chiu 2014 fall professor converters eect jssc issue msb charge

Share:

Link:

Embed:

Download Presentation from below link

Download Presentation The PPT/PDF document "– 1 – Data Converters Successive ..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.


Presentation Transcript

Slide1

– 1 –

Data Converters Successive Approximation ADC Professor Y. ChiuEECT 7327 Fall 2014

Successive Approximation

(SA) ADCSlide2

Successive Approximation ADC

– 2 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

Binary search algorithm → N*

T

clk to complete N bitsConversion speed is limited by comparator, DAC, and digital logic (successive approximation register or SAR)Slide3

Binary Search Algorithm–

3 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

DAC output gradually approaches the input voltage

Comparator differential input gradually approaches zeroSlide4

Charge Redistribution SA ADC

– 4 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

4-bit binary-weighted capacitor array DAC

Capacitor array samples input when

Φ1 is asserted (bottom-plate)Slide5

Charge Redistribution (MSB)

– 5 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014Slide6

Comparison (MSB)–

6 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

If V

X

< 0, then Vi > VR/2, and MSB = 1, C4

remains connected to V

R

If V

X

> 0, then V

i

< V

R

/2, and MSB = 0, C

4

is switched to groundSlide7

Charge Redistribution (MSB-1)

– 7 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014Slide8

Comparison (MSB-1)–

8 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

If V

X

< 0, then Vi > 3VR/4, and MSB-1 = 1, C3

remains connected to V

R

If V

X

> 0, then V

i

< 3V

R

/4, and MSB-1 = 0, C

3

is switched to groundSlide9

Charge Redistribution (Other Bits)

– 9 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

Test completes when all four bits are determined w/ four charge redistributions and comparisonsSlide10

After Four Clock Cycles…

– 10 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

Usually, half T

clk

is allocated for charge redistribution and half for comparison + digital logicVX always converges to 0 (V

os

if comparator has nonzero offset)Slide11

Summing-Node Parasitics

– 11 –

Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

If

Vos = 0, CP has no effect eventually; otherwise, C

P

attenuates V

X

Auto-zeroing can be applied to the comparator to reduce offsetSlide12

Summary of SA ADC–

12 –Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

Power efficiency – only comparator consumes DC power

DAC nonlinearity limits the INL and DNL of the SA ADC

N-bit precision requires N-bit matching from the cap arrayCalibration can be performed to remove mismatch errors (Lee, JSSC’84)

Comparator offset

V

os

introduces an input-referred offset

~ (1+

C

P

/

Σ

C

j

)*

V

os

C

P

in general has little effect on the conversion (V

X

0 at the end of the search); however, V

X

is always attenuated due to charge sharing of CPBinary search is sensitive to intermediate errors made during search – if an intermediate decision is wrong, the digitization process cannot recoverDAC must settle into ±

½ LSB bound within the time allowedComparator offset must be constant (no hysteresis or time-dependent offset)Non-binary search algorithm can be used (

Kuttner

, ISSCC’02

)Slide13

References

– 13 –

Data Converters Successive Approximation ADC Professor Y. Chiu

EECT 7327

Fall 2014

J. L. McCreary and P. R. Gray, JSSC, pp. 371-379, issue 6, 1975.

R. E. Suarez, P. R. Gray, and D. A. Hodges, JSSC, pp. 379-385, issue 6, 1975.H.-S. Lee, D. A. Hodges, and P. R. Gray, JSSC, pp. 813-819, issue 6, 1984.M. de Wit, K.-S. Tan, and R. K. Hester, JSSC, pp. 455-461, issue 4, 1993.C. M. Hammerschmied and H. Qiuting, JSSC, pp. 1148-1157, issue 8, 1998.

S.

Mortezapour

and E. K. F. Lee, JSSC, pp. 642-646, issue 4, 2000.

G.

Promitzer

, JSSC, pp. 1138-1143, issue 7, 2001.

F.

Kuttner

, ISSCC 2002, pp. 176-177.

S. M. Chen and R. W.

Brodersen

, JSSC, pp. 2350-2359, issue 2, 2006.

N.

Verma

and A.

Chandrakasan

, ISSCC 2006, pp. 222-223.

G. Van der

Plas

et al., ISSCC 2008, pp. 242-243.

M. van

Elzakker

et al., ISSCC 2008, pp. 244-245.

W.

Liu, P. Huang, and Y. Chiu , JSSC, pp

. 2661-2672,

issue 11,

2011.