Leakage in MOS devices

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Leakage in MOS devices




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Presentations text content in Leakage in MOS devices

Slide1

Leakage in MOS devices

Mohammad Sharifkhani

Slide2

Reading

Text book, Chapter III

K. Roy’s Proc. of IEEE paper

Slide3

Introduction

What is leakage?IOFF (drain current when transistor is supposed to be off)Including gate leakageWhy is it important?Stand-by power; energy consumption for no work

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Introduction

How bad is it?1nA/um @0.25um @30 degree C1uA/um @0.1um @80 degree CEach generation for a 15mm2 chipI off increase by 5xTotal Width increase by 50% Total leakage current on a chip 7.5x Leakage power 5x

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Introduction

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MOS Leakage behavior

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Leakage components

6 leakage componentsI1: PN junction reversed biasI2: Subthreshold leakageI3: Gate tunnelingI4: Hot carrier injectionI5: GIDLI6: Punchthrough

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PN junction reverse bias current

Minority carrier drift/diffusionNear the edge of depletion regionThe direct band-to-band tunnelling model (BTBT)Describes the carrier generation in the high field region without any influence of local traps. Electron-hole generation in depletion regionBand to band tunneling (BTBT) is dominant

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PN junction reverse bias current

Tunneling current density increases exponentially with doping:Na, NdVapp (drops too, minor effect)Doping increases with scalingFor typical devices it is between 10pA – 500pA at room temperature; For a die with million devicesoperated at 5 V, this results in 0.5mW power consumption  rather smallFor 0.25 μm CMOS: J = 10-100 pA/ μm2 at 25 deg C.

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Subthreshold leakage

Most important among allWeak inversionMinority carriers in the channel is small but not zeroSmall Vds; drops across the reversed-bias pn; small fieldsmall field, carrier  current is due to diffusion rather than drift (base in BJT)Wdm: maximum width of depletion layer; m<2

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When Vth is small  Vgs = 0 does not turn ‘off’ the MOS

Subthreshold leakage

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Subthreshold leakage

Exponential relationship with Vgs and Vth255mV Vth variation  3 orders of magnitude in leakageSt; milivolts/decadeThreshold voltage variation effect on leakageAbout 70-120mV/decSmaller St: sharper slopeLess voltage variation for 10x leakage increase

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Subthreshold leakage (DIBL)

Drain Induced Barrier LoweringShort channel devicesDepletion region of drain interacts with source near channel surfaceVoltage at the drain lowers the potential barrier at the sourceLowers VThIncreases subthreshold current without any change onSCauses source to inject carriers into channel surface independent of the gate voltageMore DIBL at higher VD and shorter LeffMoves curve up, to right, as VD increases

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Subthreshold leakage (Body Effect)

Vth roll offIncrease of Vth with reduction of Channel LengthReverse body biasWidens depletion regionLength ↓, Vth↑Bulk doping ↑  Vth substrate sensitivity ↑Reverse body bias ↑  Vth substrate sensitivity ↓Slope St remains the same

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IsolationsLocal Oxide Isolation (LOCOS)Trench isolationIn LOCOS, the fringing field causes the gate-induced depletion region to spread outside the channel width and under the isolationsGate has to work more to create the channel (inversion)More substantial (comparable) as the channel width decreases Increase of Vth due to narrow-channel effectKicks in for W<0.5um

Subthreshold leakage (Narrow Width Effect)

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Subthreshold leakage (Narro Width Effect)

Trench isolated technologies: – Vt decreases for effective channel widths W ≤ 0.5 μm NMOSFor PMOS: A much more complex behavior reduction of the width first decreases the until the width is 0.4 m. The width reduction below 0.4 um causes a sharp increase

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Short-channel devices: source-to-drain distance comparable to depletion width in vertical directionSource and drain depletion regions penetrate more into channel length.Part of the channel being already depleted.  Gate voltage has to invert less bulk charge to turn a transistor on.

Subthreshold leakage (Channel Length Effect)

Slide18

23 fA/um to 8 pA/umFactor of 356Smaller St:Sharper transition (worse sensitivity)Two parameters increase the subthreshold leakage as temperature is raised: 1) Vth linearly increases with temperature2) the threshold voltage decreases. The temperature sensitivity of was measured to be about 0.8 mV C.

Subthreshold leakage (Temperature Effect)

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Gate Leakage

Tox ↓  Eox ↑Two mechanisms of electron tunnelingFowler–Nordheim Tunneling: electrons tunnel into conduction band of oxide layerVery high field strength; usually not present in productsDirect Tunneling: electrons from the inverted silicon surface to the gate through the forbidden energy gap of the SiO2 layer

Slide20

Hot Carrier Injection

In a short-channel transistor, due to high electric field near the Si–SiO2 interface, electrons or holes can gain sufficient energy from the electric field to cross the interface potential barrier and enter into the oxide layer

Reliability risk! (Electrons can trap into or destroy oxide)

Increases as L drops (unless VDD drops accordingly)

Slide21

Gate-Induced Drain Leakage (GIDL)

GIDL is due to high field effect in the drain junction of an MOS transistorVg<0  Thins out the depletion region between drain to well PN junctionEffect of new electric field on the old PN depletion region  holes tunnel to substrate from drainSince the substrate is at a lower potential for minority carriers, the minority carriers that have been accumulated or formed at the drain depletion region underneath the gate are swept laterally to the substrate, completing a path for the GIDL

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The effect of GIDL is more visible at higher VDD and lower VgThinner oxide thickness and higher VDD (higher potential between gate and drain) enhance the electric field and therefore increase GIDLIncrease from 4nA  36nA (for VD from 2.7V to 4V)

Gate-Induced Drain Leakage (GIDL)

Slide23

Increasing current for negative VG values• Localized along channel width between gate and drain• Major problem in Ioff current:• Contributes to standby power, so must control this byincreasing oxide thickness, increasing drain doping, oreliminating traps.• For high performance device (low Vth), is not a majorissue.

Gate-Induced Drain Leakage (GIDL)

Slide24

When Source and Drain depletion region “touch” each other deep in the channel. Less gate influence on the currentChannel is created deeper in substrateHigher St Varies quadratically with VD and with VS

Punchthrough

Slide25

Leakage component contribution

In each region, the last term dominates

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