PPT-Diffusion Break-Aware Leakage Power Optimization and Detailed Placement in Sub-10nm VLSI

Diffusion BreakAware Leakage Power Optimization and Detailed Placement in Sub10nm VLSI Sun ik Heo Andrew B Kahng Minsoo Kim and Lutong Wang UC San Diego Samsung Electronics Co Ltd. of Electrical Engineering Princeton University NJ08544 xuningcpeh eeprincetonedu ABSTRACT Power will be the key limiter to system scalability as inter connection networks take up an increasingly signi64257cant por tion of system power In this paper Tao Lin and Chris Chu. Iowa State University. 1. Outline. Background. Problem definition. Proof of NP-Completeness. MILP formulation. Heuristic . Algorithm . Experimental results. Conclusions. 2. Background. for Power Gating Designs. Speaker: . Zong. -Wei . Syu. Dep. of EE, National Cheng Kung University. Date: . 2014/04/01. Introduction. Preliminaries . Problem Formulation. Partition Based Placement Algorithm. Andrew B. Kahng and . Hyein Lee. UC . San . Diego VLSI CAD Laboratory. Minimum Implant Area Constraint. Motivation. Prior Work. Minimum Implant Area-Aware . Placement and Sizing. Experimental Results. Sub-14nm . Constraints. Kwangsoo. Han. , Andrew B. . Kahng. and . Hyein. Lee. {. kwhan. , . abk. , . hyeinlee. }@. ucsd.edu. http://vlsicad.ucsd.edu/. ECE Department, UC San Diego. Outline. Motivation & Previous Work. Modern Algorithms. Modern global placement algorithms:. Can handle extremely large netlists. Use analytic techniques. 2. 3. Two . families: . Modern Algorithms. Quadratic . placers. Non-convex . optimization placers . A View Forwards Through Fog. Mark Rodwell, UCSB. Plenary, Device Research Conference, June 22, 2015, Ohio State. InP HBT:. J. Rode**, P. Choudhary, A.C. Gossard, B. Thibeault, W. Mitchell: . UCSB . M. Urteaga, B. Brar: . S. . Kaxiras. , M . Martonosi. , “Computer Architecture Techniques for Power . Effecience. ”, Chapter 5.. Static Power. Remember:. Has increased to a significant % of total power consumption.. Seen in older technologies, but CMOS prevents open paths from . Tufts University. Instructor: Joel . Grodstein. joel.grodstein@tufts.edu. Lecture 6: Discrete voltage and frequency switching. DVFS. What we’ll cover. DVFS: why we care. What is DVFS. Effects on clocking. Tufts University. Instructor: Joel . Grodstein. joel.grodstein@tufts.edu. Lecture 7: Dark silicon. Resources. The future of microprocessors. , . Shekhar. . Borkar. 2011. “The past 20 years were the ‘great old days’; the next 20 years will hopefully be the ‘pretty good new days’ ”. EE 194 Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel.grodstein@tufts.edu Lecture 2: Moore's Law, Scaling and power Technology scaling Everyone has heard of Moore’s Law. It’s probably been mentioned in most newspapers at some point. But what does it really mean? Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints Kwangsoo Han , Andrew B. Kahng and Hyein Lee { kwhan , abk , hyeinlee }@ ucsd.edu http://vlsicad.ucsd.edu/ ECE Department, UC San Diego OOF - Valet. 2. Goal of This Presentation. Introducing our proposal: ONAP-OOF/placement-optimization (Codename, Valet). Possible required . implementation in . MultiCloud. for the placement-optimization. Kahng. ‡, . Minsoo Kim. ‡, . Lutong. Wang‡ and . Chutong. Yang‡ . ‡UC San Diego, †Samsung Electronics Co., Ltd.. Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI.