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Radiation tolerance of 65 nm Radiation tolerance of 65 nm

Radiation tolerance of 65 nm - PowerPoint Presentation

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Radiation tolerance of 65 nm - PPT Presentation

technology Sandro Bonacini CERN PHESEME sandrobonacinicernch O utline Test description Type of devices under test Measurement setup amp conditions Total Ionizing Dose effects results ID: 720065

sandro bonacini ese cern bonacini sandro cern ese devices test current shift leakage radiation max 130nm digital mrad pmos voltage technology narrow

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Slide1

Radiation tolerance of 65 nm technology

Sandro Bonacini

CERN PH/ESE/ME

sandro.bonacini@cern.chSlide2

OutlineTest descriptionType of devices under testMeasurement setup & conditions

Total Ionizing Dose effects results

Threshold voltage shift

Leakage currentTransconductance reduction Aggregated effects on digital structuresSingle-Event Upset measurement resultsSEU, MBUPresent work & future plans

2

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.chSlide3

Test structures, measurement setupOne chip with digital logicAssembled with foundry standard cells, pads and IP blocks

Packaged, functional tests & irradiation measurements run on a custom test board

Shift-register

64 kbitRing oscillator1025 invertersSRAM (from foundry compiler)56 kbitIrradiation up to 200

Mrad X-rays while operatingOne chip with devices and analog structuresTransistor devices

Irradiation & measurement at

probe station, no bonding

Analog blocksPreamplifierDiscriminatorBinary weighted DACSub-binary radix DACIrradiation up to 200 Mrad X-rays under worst-case static bias

Test devices

Analog structures

SRAM

Shift-register

Ring oscillatorSlide4

TID effects on CMOS technologySandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

4

Bird’s beak

Field oxide

Parasitic MOS

Parasitic channel

Source

Drain

1. Effects in the thin gate oxide

2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor

Threshold voltage shift

Leakage currentSlide5

Core NMOS radiation performanceSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

5

Up to ~20mV shift for 200

MradSome rebound effect visible for narrow devicesin 130nm: was 150mV

At high doses Vth shift is positive for wide devices, negative for narrow devicesSTI edge oxide traps considerable charge (RINCE)

Subtreshold

slope does not change significantly

Less than 10× increase in leakage for wide devices (W > 360nm)

Narrow devices have up to 2.5 orders of magnitude increase

Threshold voltage shift

Leakage currentSlide6

Core NMOS, leakage vs spreadSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

6

Radiation-induced leakage variation is comparable to transistor parameter spread

Parameter spread 1

σSlide7

Core NMOS, leakage currentSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

7

65nm has better performance with respect to 130nm: (Plots are in the same scale)

a rebound effect is visible in 130 nm:all 130nm devices are peaking at ~100nANarrow devices increase

Ileak by 3 orders of magnitudeI

leak

is ~1nA @136

Mrad

130 nm

65 nm

10

8

10

7

TID [rad]

10

6

F.Faccio

et al., “

Radiation-induced edge effects in deep submicron CMOS transistors”, IEEE Tr.

Nucl. Sci. 2005Slide8

I/O NMOS radiation performanceSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

8

Vth

shift is positive at high dosesUp to ~200mV for 200 Mrad

Vth,0 is ~500mVInterface states seem to dominate over trapped charge

Some rebound effect visible for narrow devices

Bigger shift for narrow devices

Similar to 130nm max 170mV @136Mrad

Increase in leakage by 2 orders of magnitude

Most around 1 Mrad, then saturates

No rebound within 200 MradEnclosed Layout Transistor (ELT) structure is advised

Threshold voltage shift

Leakage currentSlide9

I/O NMOS, leakage currentSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

9

Comparison with 130nm: (Plots are in the same scale)

devices had Ileak peaking at 1uA @ 2Mrad

had ~5-6 orders of magnitude increase Similar

current 100pA@136Mrad

90 nm technology looks like 130nm (same foundry)

130 nm

65 nmSlide10

Core PMOS, threshold voltage shiftSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

10

PMOS

Vth shift limited to 60 mVtrapped charge and interface states sum upMore evident for narrow devicesLess than 10mV for transistors with W>1um

Compared to other technologiesBetter performance than 130 nm

had up to 90mV @136Mrad

30mV for wide devices

In a 90 nm tech we observed a similar effect: 70mV @ 200MradSlide11

Core PMOS, gm,max reductionSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

11

Radiation kills maximum

g

m,max

(strong inversion)

...but not g

m in weak inversion regionCould influence the speed of digital logic

Affects only PMOS

gm,max

Max. drive currentSlide12

I/O PMOS, threshold voltage shiftSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

12

Considerable shift of the threshold voltage

Up to 800 mV (+160%) for 200 MradVth0

is ~550mVMore pronounced for narrow channel transistorsDevices turn offDesign must be oversized

Worse performance than in 130nm

Had max 450mV shift @136Mrad

Similar to 90 nmSeen 600mV @200 MradSlide13

I/O PMOS, gm,max reductionSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

13

Similar effect on

g

m,max

in strong inversion as seen for core devices

Maximum drive current is greatly reduced due to Vth and

gm decreaseNecessary to oversize transistors

g

m,max

Max. drive currentSlide14

Digital test structures: SRAM, S-RSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

14

Measured static and dynamic currents of SRAM and shift-register

Dynamic test run @ 30MHzSRAM static current increases by 300×Dynamic current reflects this change with a small increase

Ultra-narrow devices are used in the SRAM from foundry (W=80nm) Peak current at ~2-3 Mrad

Dependent on dose rate (?)

Dose [×100

Mrad

]

Shift-register static current changes very little

Dynamic current practically constant (decrease!)

~12.5

nW/MHz per D-FFVisible partial annealing effect at room temperatureTime constant ~ 1.5 hours

annealing 25 °C

13.8 hours

annealing25

°C

annealing

100 °C, 1 weekSlide15

Digital test structures: ring-oscillator

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

15

Ring oscillator

Logic slows down with radiation-13.8%Must keep margin in digital design

…or select cells with wider transistors

Due to PMOS drive current reduction

Current and speed remain proportional~ 3 nW/MHz for 1 inverter

Annealing

100 °C, 1 weekSlide16

SEU test results, tech. comparisonSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

16

65nm seems to saturate at a cross-section 3.4× smaller than 130nm

About proportional to 4× area reduction90nm registers were custom-made (not standard cells)Higher saturation cross-section though area is ½ of cell in 130 nm

LET thresholds are less than 1.1 MeVcm2/mg for all technologiesNote: SEU-robust cells are well below 10-10

cm

2

/bitSlide17

Multiple Bit Upsets (MBUs) in SRAMSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

17

Plots above are @1.2V supply

Most MBUs occur in adjacent cells along n-wells (SRAM cell is ~1.0x0.5um)

(...along bit-lines and not along word lines, due to internal SRAM structure)

Lower power supply worsens MBU contribution (up to 7-BU @0.9V, 0 deg)

Shift-register MBUs are <1% (2-BU and 3-BU were seen)

LET = 20.4 MeVcm2/mg (Ar, 60 deg tilt)Slide18

MPW 26 November 2012Test chip with several ring oscillators made of library inverters of different size

… to test the impact of TID on the speed of logic gates

DICE cell SEU test chip

Demonstrators:Low-power SEU-robust serializer 4.8 Gb/sCLICpix, imager with 25um pixel size

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.chSlide19

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Thank you…

65 nm demonstrates a better radiation hardness than previous generation technologies

No ELT for digital logic

…but wide PMOSes help limiting drive/speed loss

I/O devices still need ELT

PMOS might need to be oversized

SEU performance is better as sensitive areas are smallerBut beware in using more logic in chipsMore evident MBUsAdditional information can be found in “Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

”, V.Re, L.Gaioni, M.Manghisoni

, L.Ratti, G.Traversi

, IEEE Tr. Nucl. Sci., Vol.57,

No.6, Dec. 2010Future plansDesign CMOS I/O standard pad library

Select cells in standard cell library from foundry with devices WPMOS > 500nm (TBD)

MPW in Nov. 2012TID std. cell test structures, DICE SEU test, ClicPix, Low-power GBT19Slide20

20Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Thank YouSlide21

SEU test results – heavy ion beamSandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

21

No substantial differences between static test and dynamic test run at 30 MHz

Evidence of 1 clock root SEU hitSRAM cell is 13× smaller than DFF

Max 1.7× increase in cross-section with reduced power supply voltage @ 0.9VSlide22

PDK, metal stack and libraries22

Integrate OA PDK and library to form a M/S kit

One metal stack and one library delivered at first

4 thin + 2 thick no mimcaps included by defaulttcbn65lp

Available later (TBD):Second option of metal stack

3 thin + 2 thick

Second option for library

tcbn65lpbwp7thvt

STI

poly

M2

M1

M3

M5

M6

M4

M1

W

M2

M3

M4

RDL

M5

M4

M5

poly

M2

M1

M3

M1

W

M2

M3

W

M6

RDL

passivation

M1

W

M1

W

Many tech. options but they all come at a cost

Thin metals are expensive because of their fine pitchSlide23

Rad-hard CMOS I/O pad library23

Standard I/O pad library from

foundry suffers

from radiation effectsUse of 2.5V-rated transistors with >5-nm-thick gate oxideNMOS leakagePMOS tend to turn off + loss in

transconductance~50% loss in maximum drive current within 200 Mrad

Speed reduction

Radiation hardened I/O pad library

Rated for 1.2 VOnly core devices, thin gate oxideBetter radiation performanceTo be packaged together with the OA M/S design kitSlide24

MotivationFuture vertex detectors for high energy physics experiments can benefit from modern deep submicron technologiesScaling is necessary to improve the performances of pixel detectors

Smaller pixel sizes (pitch)

More “intelligence” in each pixel

Faster serializersIn general, the expected advantages in porting a front-end circuit to a more advanced technology include

A much more compact, faster digital part (reduction in area of ~60% compared to 130nm technology)

Lower noise equivalent charge, due to the reduced capacitances associated with smaller pixels

Better matching than in 130nm

Studies on radiation hardness of the selected technology are neededA set of test chips was designed, fabricated and tested to assess radiation hardness and functionality of both analog and digital test structuresSandro Bonacini - PH/ESE - sandro.bonacini@cern.chSlide25

Drawbacks of 65 nmHigher cost of tape-out compared to older technologiesStrong push for 1st working silicon

Push for more IP re-usage

?

Must limit technology options usageHigher gate leakage current

More stringent design rules: ELT transistors are not allowed, more difficult to achieve an optimal layout.OPC rules: avoid jogs, zigzag, shapes like “L”, “U” or ring, …Deep submicron technologies are not optimized for analog designs

Smaller dynamic range due to the lower power supply (1.2 V) reduces the possibilities to use some structures (such as

cascoded

stages). Multiple stages, with possible stability issues, are needed to achieve a high gain.This problem is moreover aggravated by the lower output resistance of the MOSFETs which lowers the gain of the single stages.

65nm technology

130nm technology

Minimum gate length

60nm

120nm

Metal layers

10

8

Power supply

1.2 V - 1.0 V

1.5 V - 1.2 V

Gate leakage

350

pA

/

μ

m

2

20

pA

/

μ

m

2

Channel leakage (at minimum length)

211

pA

/

μ

m

400

pA

/

μ

m

Typical transistor leakage (minL,3minW)

84

pA

290

pA

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

25