PPT-FLEXclusion: Balancing Cache Capacity and On-chip Bandwidth via Flexible Exclusion

Jaewoong Sim Jaekyu Lee Moinuddin K Qureshi Hyesoon Kim Outline Motivation FLEXclusion Design Monitoring amp Operation Extension Evaluations Conclusion Introduction Todays processors have multilevel cache hierarchies. Gigascale. DRAM caches. Chiachen Chou, Georgia Tech. Aamer. . Jaleel. , NVIDIA*. Moinuddin. K. . Qureshi. , Georgia Tech. ISCA 2015. Portland, OR. June 15 , 2015. 3D DRAM Helps Mitigate Bandwidth WALL. Architectures through Adaptive Wavelength Division. Multiplexing. Benjamin C. . Johnstone. , Dr. Sonia Lopez Alarcon. 1. Background. Problem Statement. Methodology. Speedup and Detailed Analyses. Results. Varun. . Mathur. Mingwei. Liu. 1. I-cache and address tag . Instruction cache has. Large chip area. High access frequency=>switching power. Example:. Direct mapped I-cache. 1024 entries (=>1024 one way sets). Off-Chip Power-Area-Timing Models. Norman P. . Jouppi. ¥. , Andrew B. Kahng. †‡. ,. Naveen Muralimanohar. ¥. , . Vaishnav Srinivas. †. November 6. th. , 2012. ECE. †. and CSE. ‡. Departments. Memory Wall . The . growing disparity of speed between CPU and memory outside the CPU . chip. Bandwidth wall: limited . communication bandwidth beyond chip . boundaries. Solution . Memory hierarchy . Network Performance Measurement. Srinivas Narayana. MIT CSAIL. An example: High tail latencies. Delay completion of flows. (and applications). An example: High tail latencies. Where is the queue buildup?. . . Presented by:. . Gary Dorris, PhD. . gdorris@ascendanalytics.com. 303.415.0311. . June 8, 2017. Questions Addressed. How does . PowerSimm. identify capacity and capacity attribute needs for an individual utility and for the region? How does it differ from how other modeling tools identify needs? . CACTI-IO: CACTI With Off-Chip Power-Area-Timing Models Norman P. Jouppi ¥ , Andrew B. Kahng †‡ , Naveen Muralimanohar ¥ , Vaishnav Srinivas † November 6 th , 2012 ECE † and CSE ‡ Departments Language-Directed Hardware Design for Network Performance Monitoring Srinivas Narayana, Anirudh Sivaraman , Vikram Nathan, Prateesh Goyal, Venkat Arun , Mohammad Alizadeh , Vimal Jeyakumar Vinson Young. Prashant Nair. Moinuddin Qureshi. 1. MOORE’s LAW HITS BANDWIDTH WALL. 2. Moore’s scaling encounters Bandwidth Wall. 3D-DRAM MITIGATES BANDWIDTH WALL. 3. 3D-DRAM. Hybrid Memory Cube (HMC) from Micron, . Xiangyao. Yu. 1. , Christopher Hughes. 2. , . Nadathur. Satish. 2. , . Onur. Mutlu. 3. , Srinivas . Devadas. 1. 1. MIT . 2 . Intel Labs . 3. ETH Zürich. Motivation. In-package DRAM has . Mohammad Laghari and Didem Unat. 1. SBAC-PAD 2017 @ Campinas, Brazil 17-20 October 2017. https://parcorelab.ku.edu.tr. Image taken from: http://www.amd.com/en/technologies/hbm. Introduction. To overcome memory bandwidth limitations, multiple memories with different characteristics are introduced. Distributed Auto-Tuning. Samuel . Williams, Leonid . Oliker. Jonathan Carter, John . Shalf. 1. Lawrence Berkeley National Laboratory. . SWWilliams@lbl.gov. Introduction. Management of . data locality and data movement .