Wireless Embedded Systems Aaron Schulman CSE190 Winter 2020 Lecture 8 Direct Memory Access Reminder: Midterm next week Will evaluate your understanding of concepts needed to implement the first project Architecture of microcontrollers
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Wireless Embedded Systems
Aaron Schulman CSE190 Winter 2020
Lecture 8
Direct Memory Access<br>
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Reminder: Midterm next week Will evaluate your understanding of concepts needed to implement the first project
Architecture of microcontrollers (peripherals, MMIO, RAM)
Timers
GPIO
Implementing and debugging firmware (and reading datasheets)
Will evaluate your understanding of serial communication:
Digital communication: how do we move bits over wires
SPI, I2C, UART<br>
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How do you move data to and from peripherals in MMIO? Moving data to a peripheral? - CPU instructions that write data from RAM to MMIO
SPI->DATA = X[1];
Moving data from a peripheral?
CPU instructions that read MMIO to RAM
X[2] = SPI->DATA;<br>
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Why do we need DMA?<br>
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Why do we need DMA? Polling and Interrupt driven I/O concentrates on data transfer between the processor and I/O devices.
An instruction to transfer (mov datain,R0) only occurs after the processor determines that the I/O device is ready
Either by polling a status flag in the device interface or
Waits for the device to send an interrupt request.
Considerable overhead is incurred, because several program instructions must be executed for each data word transferred.<br>
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Why do we need DMA? Moving things is a waste of CPU instructions:
Instructions are needed to increment memory address and keeping track of how many bytes are moved.<br>
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Direct Memory Access (DMA) To transfer large blocks of data at high speed, an alternative approach is used, called DMA.
Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.
It’s just another peripheral, but it’s only job is moving data.<br>
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DMA Controller DMA controller is connected to the internal I/O bus.
Performs the functions that would normally be carried out by the processor when access main memory. For each word transferred, it provides the memory address and all the bus signals that control data transfer.<br>
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The DMA Transaction in a nutshell Device wishing to perform DMA asserts the processors bus request signal.
Processor completes the current bus cycle and then asserts the bus grant signal to the device.
The device then asserts the bus grant ack signal.
The DMA device performs the transfer from the source to destination address.
Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
Processor acknowledges the bus release and resumes its bus cycles from the point it left off.<br>
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Use of DMA Controllers DMA controller Processor Bus control logic RAM GPIOs Storage 3. Data is transferred 2. DMA controller requests transfer to memory 1. CPU sets up a memory transaction on the DMA controller 4. ACK 5. Interrupt when done<br>
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Buffers and Arbitration Most DMAs have a data storage buffer – peripherals can send a burst of data faster than main memory can handle (as long as this happens infrequently)
Bus Arbitration is needed to resolve conflicts with more than one device (2 DMAs or DMA and processor, etc..) try to use the bus to access main memory.<br>
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Bus Arbitration Bus Master – the device that is allowed to initiate bus transfers on the bus at any given time. When the current master relinquishes control, another device can acquire this status.
Bus Arbitration – the process by which the next device to become bus master is selected and bus mastership is transferred to it.<br>
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Arbitration Approaches Centralized – a single arbiter performs the arbitration.
Distributed – all devices participate in the selection of the next bus master.<br>
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How is OS involved I/O operations are always performed by the OS in response to a request from an application program.
OS is also responsible for suspending the execution of one program and starting another.
OS puts the program that requested the transfer in the Blocked state,
initiates the DMA operation,
starts execution of another program.
When the transfer is complete, the DMA controller informs the processor by sending an interrupt request.
OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.<br>
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DMA is possible because of linear memory addressing<br>
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Memory Architecture<br>
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Physical vs Virtual Memory Two memory “spaces”
Virtual memory space what the program “sees”
Physical memory space what the program runs in (size of RAM)
Virtual memory requires
Dedicated hardware on CPU chip called Memory Mgmt Unit (MMU)
Cooperation between CPU hardware & operating system 17 Source: Bryant & O’Hallaron<br>
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Example: Virtual and Physical Address Space 18 bne 0x00 add r10,r1,r2 sub r3,r4,r1 sw r5,0x0c 0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C 0x00
0x04
0x08
0x0C add r1,r2,r3 sub r2,r3,r4 lw r2, 0x04 mult r3,r4,r5 add r1,r2,r3 sub r2,r3,r4 lw r2, 0x04 mult r3,r4,r5<br>
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Cache coherency problems Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X, assuming a write-back cache. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.<br>
