Phase2 pixel electronics - PowerPoint Presentation

Slide1

Phase2 pixel electronics

Jorgen Christiansen, CERN PH-ESE

1

Time: Thursday 15:00, Biweekly

Specific meeting theme or General status chat as needed

2

Regular pixel electronics meeting

Pixel electronics system

 (overlap with detector layout, optimization, mechanics)

System configuration: Number and types of modules, Number of chips, links, power consumption, etc.Services: Readout cables, control cables, power cables, opto-modules, optical links, (cooling)Pixel chip (overlap with RD53)CMS requirements to pixel chipPixel chip readout and control interface for use in CMS.Power consumption in different configurations and settingsInterface to pixel sensor(s)Bump-bonding issues.Simulations with CMS MC data and estimation of required readout rates (and appropriate formatting/compressions)Radiation tolerance.Test and verification of pixel chip for CMS(Dedicated CMS phase 2 pixel chip)Production and production testingPixel module electronics (overlap with pixel sensor, mechanics, cooling, etc.)Module types and configurationPixel module electronics design: HDI, wire bonding, local decoupling, connectors, etc.Power dissipationTest and verification of pixel module functionalityReliability optimization and verificationProduction and production testing

Serial powering

( overlap with shunt-LDO development and simulations within

RD53)

Configuration

and optimization of serial powering for CMS.

Power

cables and connectors

Test

and evaluation of serial powering (with FEI4 chips and later with

RD53A)

Failure

scenarios and schemes to deal with this.

Off

detector power supplies with racks and

infrastructure

Readout/control

E-links

between pixel chip and LPGBT (number of links per chip/module, cables,

connectors)

LPGBT

based

opto

conversion module: design, test,

production

Optical

links

Production and test: E-link cables,

Opto

conversion

module

Test systems

and

DAQ interface

(overlap with RD53 and synergy with CMS outer tracker to be determined)

Test

system(s) for pixel chip, pixel modules, test beams

Hardware

, firmware, software ( and required support)

Final

off-detector DAQ interface ( in common/synergy with CMS outer tracker)

Off-detector

Racks and infrastructure

New RD53 working group.

Assure availability of test system(s) when RD53A available: ~summer 2017Testing:Debug and functional test of RD53ARadiation testing of RD53A

Testing of RD53A with Sensor

Test beams with RD53A

Coming version(s) of RD53 pixel chip

Production testingTest system

HardwareFirmware (FPGA)SoftwareSupport/documentation to users (could be many)What test system(s) ?One good, flexible, reliable test system for allDedicated test systems for different usages.One for ATLAS, One for CMSFirst WG meeting Oct. 20 at 16:00Let me know if CMS groups interested/willing to contribute3Pixel chip readout and test system

Pixel chip size:

Adapt chip to system/layout: ~16mm x 22mmA

dapt system/layout to available chip.

R

eadout links: Rate, Number, Length & Material

Rate per link: 1.28Gbits/s

Required readout bandwidth depends on:Chip size, Pixel size and shape, Sensor thickness, Layer (r), location (z), radiation damage, , ,Current MC simulations: ~3GHz/cm2 No safety factor applied on top of PU=200.Max hit loss < 1% and degrading gracefully at higher ratesTrigger rate:750kHzReadout data formatting and compressionCable type: Twisted with or without shield, Capton (Alu or Cu)Adaptation of links per pixel module and links per LPGBT (module).Serial powering:Chips in parallel: 4 (2), critical when considering failure scenariosNumber of modules in chainRequired current (~10uA/pixel, 1.2v) + current margin (25%): ~12uA/pixel, SLDO input voltage: ~1.5v. Total power ~20uW/pixel -> ~0.8W/cm2 ( <1W/cm2)Thermal issues (seems OK, Yadia) and failure scenarios4Major system issues/questions

Common “RD53”

or dedicated CMS / ATLAS chipsCurrent CMS pixel chip size: ~16mm x 22mmConstraints: Multiple of 8 pixels per side, ~2mm height EOC, (20mm width of EOC)

Generic RD53 chip: ~20x22mm

2

(400 x 400 pixels + EOC)

RD53A: 20x11.8mm2 (400 x 192 pixels), constrained by reticle

sharingDetector layout enforce specific pixel chip size ?r1 CMS: 30mmr1 ATLAS: 40mm (or 30mm ?)Hit rate scales as r2 (1.5 effect)Barrel length, disk rings, etc.Difference in trigger architecture/rateATLAS reviewing trigger architecture, but still hope that it can be “compatible” with CMSDifference in readoutCMS: Short (<1m), multiple (<=4) 1.28Gbits/s to LPGBT (10Gbits/s)ATLAS: Long ( 5-6m), 5Gbits/s, remote laser driverExcluded to have common ATLAS/CMS chip ?.Do we (RD53/CMS) have enough experienced chip designers to design/verify/test two different chipsAdditional 1M$ engineering run(s)Too risky to have the two experiments with same chip ?Final decision on this to be made ~end 2017.Backup development of CMS pixel chip @ PSI in 110um (tracker review)Get presentation of this when possible5CMS specific pixel chip.

Part 1 (Executive summary) :

~9 pages for phase 2 pixel2-3 pages on pixel electronics (Jorgen)Outline of pixel electronics architecture with summary of number of chips, modules, links, power.

Part 2 (Technical “details”):

~20 pages for phase 2 pixel

Pixel chip: 4 pages (Jorgen)

Architecture of RD53 chip, Radiation test results, results from prototyped test circuits and small pixel arrays (FE65-P2, CHIPICs).

Simulation results with current MC data.Power estimation and power simulations.Plans of RD53A chip (and CMS specific chip ?)Backup solution in 110nm ?Readout links: 1 page (Jorgen)Options for E-links and studies/simulations made of this.Mapping to LPGTB and outline of LPGBT moduleSerial power: 2 pages (Giacomo)Outline of serial powering with 2-4 chips in parallel and modules in series.Simulations of serial power chain.Refer to working serial powered pixel stave using FEI4 (ATLAS work)Handling failures and power up/downOverview of serial power system: chains, currents, total power and losses, power suppliesPlanned R&DThis is really (too) short (as short as TP)6TDR