– 1 – Data Converters DAC Professor Y. Chiu - PowerPoint Presentation

Slide1

– 1 –

Data Converters DAC Professor Y. ChiuEECT 7327 Fall 2014

DAC ArchitectureSlide2

DAC Architecture–

2 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Nyquist DAC architectures

Binary-weighted DAC

Unit-element (thermometer-coded) DAC

Segmented DAC

Resistor-string, current-steering, charge-redistribution DACs

Oversampling DAC

Oversampling performed in digital domain (zero stuffing)

Digital noise shaping (

ΣΔ

modulator)

1-bit DAC can be used

Analog reconstruction/smoothing filterSlide3

– 3 –

Data Converters DAC Professor Y. ChiuEECT 7327 Fall 2014

Binary-Weighted DACSlide4

Binary-Weighted CR DAC–

4 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Binary-weighted capacitor array

→ most efficient architecture

Bottom plate @ V

R

with b

j

= 1 and @ GND with b

j

= 0

C

u = unit capacitanceSlide5

Binary-Weighted CR DAC–

5 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

C

p

→

gain error (nonlinearity if C

p

is nonlinear)

INL and DNL limited by capacitor array mismatchSlide6

Stray-Insensitive CR DAC–

6 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Large A needed to attenuate summing-node charge sharingSlide7

MSB Transition–

7 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Largest DNL error occurs at the midpoint where MSB transitions, determined by the mismatch between the MSB capacitor and the rest of the array.

Code 0111

Code 1000Slide8

Midpoint DNL–

8 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

δ

C > 0 results in positive DNL

δ

C < 0 results in negative DNL or even nonmonotonicity

δ

C > 0

δ

C < 0Slide9

Output Glitches–

9 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Glitches cause waveform distortion, spurs and elevated noise floors

High-speed DAC output is often followed by a de-glitching SHA

Cause: Signal and clock skew in circuits

Especially severe at MSB transition where all bits are switching –

0111…111

→

1000…000Slide10

De-Glitching SHA

– 10 –

Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

SHA output must be smooth (exponential settling can be viewed as pulse shaping

→ SHA BW does not have to be excessively large

).

SHA samples the output of the DAC after it settles and then hold it for T, removing the glitching energy.Slide11

Frequency Response–

11 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014Slide12

Binary-Weighted Current DAC

– 12 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Current switching is simple and fast

V

o

depends on R

out

of current sources without op-amp

INL and DNL depend on matching, not inherently monotonic

Large component spread (2

N-1

:1)Slide13

R-2R DAC–

13 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

A binary-weighted current DAC

Component spread greatly reduced (2:1)Slide14

– 14 –

Data Converters DAC Professor Y. ChiuEECT 7327 Fall 2014

Unit-Element DACSlide15

Resistor-String DAC–

15 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Simple, inherently monotonic

→ good DNL performance

Complexity

↑ speed ↓ for large N, typically N ≤ 8 bitsSlide16

Code-Dependent Ro

– 16 –

Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

R

o

of ladder varies with signal (code)

On-resistance of switches depend on tap voltage

Signal-dependent

R

o

C

o

causes HDSlide17

DNL–

17 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014Slide18

INL–

18 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014Slide19

INL and DNL of BW DAC–

19 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

A BW DAC is typically constructed using unit elements, the same way as that of a UE DAC, for good component matching accuracy.Slide20

Current-Steering DAC–

20 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Fast, inherently monotonic

→ good DNL performance

Complexity

increases for large N, requires B2T decoderSlide21

Unit Current Cell–

21 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

2

N

current cells typically decomposed into a (2

N/2

×

2

N/2)

matrix

Current source cascoded to improve accuracy (R

o

effect)Coupled inverters improve synchronization of current switchesSlide22

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Data Converters DAC Professor Y. ChiuEECT 7327 Fall 2014

Segmented DACSlide23

BW vs. UE DACs–

23 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Binary-weighted DAC

Pros

Min. # of switched elements

Simple and fast

Compact and efficient

Cons

Large DNL and glitches

Monotonicity not guaranteed

INL/DNL

INL(max) ≈ (√N/2)

σ

DNL(max) ≈ 2*INL

Unit-element DAC

Pros

Good DNL, small glitches

Linear glitch energy

Guaranteed monotonic

Cons

Needs B2T decoder

complex for N

≥ 8

INL/DNL

INL(max) ≈ (√N/2)

σ

DNL(max) ≈

σ

Combine BW and UE architectures → SegmentationSlide24

Segmented DAC–

24 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

MSB DAC: M-bit UE DAC

LSB DAC: L-bit BW DAC

Resolution: N = M + L

2

M

+L switching elements

Good DNL

Small glitches

Same INL as BW or UESlide25

Comparison–

25 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Example

: N = 12, M = 8, L= 4,

σ

= 1%

Architecture

σ

INL

σ

DNL

# of s.e.

Unit-element

0.32 LSB’s

0.01 LSB’s

2

N

= 4096

Binary-weighted

0.32 LSB’s

0.64 LSB’s

N = 12

Segmented

0.32 LSB’s

0.06 LSB’s

2

M

+L = 260

Max. DNL error occurs at the transitions of MSB segmentsSlide26

Example: “8+2” Segmented Current DAC

– 26 –

Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Ref: C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm

2

,”

IEEE

Journal of Solid-State Circuits

, vol. 33, pp. 1948-1958, issue 12, 1998.Slide27

MSB-DAC Biasing Scheme–

27 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

Common-centroid global biasing + divided 4 quadrants of current cellsSlide28

MSB-DAC Biasing Scheme–

28 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014Slide29

Randomization and Dummies

– 29 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014Slide30

References–

30 –Data Converters DAC Professor Y. Chiu

EECT 7327

Fall 2014

M. J. M.

Pelgrom

, JSSC, pp. 1347-1352, issue 6, 1990.

D. K. Su and B. A.

Wooley

, JSSC, pp. 1224-1233, issue 12, 1993.

C.-H. Lin and K.

Bult

, JSSC, pp. 1948-1958, issue 12, 1998.

K. Khanoyan, F. Behbahani, A. A.

Abidi, VLSI, 1999, pp. 73-76.K. Falakshahi, C.-K. Yang, B. A. Wooley, JSSC, pp. 607-615, issue 5, 1999.

G. A. M. Van Der

Plas

et al., JSSC, pp. 1708-1718, issue 12, 1999.

A. R.

Bugeja

and B.-S. Song, JSSC, pp. 1719-1732, issue 12, 1999.

A. R.

Bugeja

and B.-S. Song, JSSC, pp. 1841-1852, issue 12, 2000.A. van den Bosch et al., JSSC, pp. 315-324, issue 3, 2001.