Experiment 8 What You May Have Missed Continued use of structural modeling VHDL behavioral models Best approach for sequential circuits VHDL model for memory D and T flipflops Synchronous and asynchronous control ID: 721815
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Slide1
Digital Alarm System
Experiment 9Slide2
Experiment 8: What You May Have Missed
Continued use of structural modeling
VHDL behavioral models
Best approach for sequential circuits
VHDL model for memory
D and T flip-flops
Synchronous and asynchronous control
More complex circuitry creation
less boring than the usual stuff Slide3
Experiment 8: Questions
How would you implement a T flip-flop using a D flip-flop and some additional logic gates? Draw the circuit for this in your report.
What were the operational characteristics of the circuit used in Procedure 2. In other words, completely describe the operation 4-bit counter used in this procedure.
What output is displayed when the count value is greater than nine? Why is this? Is this a problem?
What were the operational characteristics of the circuit used in Procedure 3. In other words, completely describe the operation of the circuit used in this procedure.
Slide4
Experiment 8: Random Notes
Timing diagrams need to be annotated
it’s not the reader’s job to figure out what is going on or what is important
Don’t forget circuit diagrams
circuits you designed/experimented with
answers to questions
Take more space: use blank lines in code and in experiment write-upSlide5
Instructional Objectives:
Using VHDL behavioral modeling in the design of a Finite State Machine (FSM)
To combine previously designed VHDL modules into a complete digital alarm system using structural modelingSlide6
Sequential Storage Elements
Storage elements in digital logic are sequential components whose output(s) are a function of both the current state and current input(s).Slide7
Finite State Machine
A Finite State Machine (FSM) is a digital circuit whose state changes based on both the current state (of the FSM) and the current inputs
The outputs of a FSM are functions of the current state (Moore Model) --or-- functions current state and current inputs (Mealy Model)
Synchronous FSMs change their state with respect to a clock input and maintain their state (store their state) in flip-flopsSlide8
FSM Models
Standard Architecture
VHDL Behavioral ModelSlide9
VHDL Behavioral Models for FSM
VHDL Dependent PS/NS Architecture:
Next State Sequencing
Output Decoder
X’s
External Control
(CLR, En, PRE)
State Memory
Clock Edge
Synchronization
Ext. Controls
(clr, en, preset)
Z’s
Ref: Low-Carb VHDL Tutorial
CPE 169 Experiment 9
Dependent PS / NS Coding Style:
(2 Processes)
Synchronous Process
Clocking / Control (clears, enables, presets)
Combinatorial Process
Next State Sequencing
Output Decoding Logic
Y’sSlide10
FSM Models
Structural Model
Component
ComponentSlide11Slide12
Experiment 9 Overview
P1: Finite State Machine Design
Using Your State Transition Diagram & PS/NS Table
Using the “Dependent PS/NS” VHDL Architecture
Simulate to Verify (Test Cases?)
P2: Digital Alarm System
Integrate earlier modules into a working system
Verify the complete system (instructor signoff)
Detailed schematic
!!Slide13
Alarm Finite State Machine
State Transition Diagram
UNARMED
Sys_
Armed
=0
Alarm
= 0
ARMED
Sys_
Armed
Alarm
= 0
ALARM
Sys_Armed
=0
Alarm
= 1
0,
-
d
-
1,
-
d
-
0, 1
1,
-
d
-
0, 0
0,
-
d
-
1,
-
d
-
=1
Sys_On_L, Break_In
SOUNDINGSlide14
Present State Next State Table
Present State Present Input Next State Present Output
Q1 Q0 OFF/ON BREAKIN Q1* Q0* armed alarm
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 . .
0 1 . .
0 1 . .
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
When your PS/NS Table is complete, obtain next state equations for Q1* and Q0* as functions of the current state (Q1 and Q0) and the current input (OFF/ON, BREAKIN) using a K-map. Equations for the output can be obtained by inspection.Slide15
FSM in VHDL
ARCHITECTURE mysolution
OF
myFSM
IS
SIGNAL Q1, Q0: STD_LOGIC;
BEGIN
PROCESS
(clk,Q1, Q0, offon, breakin )
BEGIN
IF (rising_edge(clk)) THEN
Q1 <=
next state equation for Q1;
Q0 <=
next state equation for Q0;
END PROCESS;
alarm <=
output equation for alarm signal;
armed <=
outputequation for armed signal;
END
mysolution
;