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Fabrication Process Options - PowerPoint Presentation

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Fabrication Process Options - PPT Presentation

Gary Varner Specification Details are often Application Specific Is IBM 130nm always the best choice 1 6OCT2010 Electronics GPC Review 2 An example app single g timing Belle II imaging TOP ID: 480233

tsmc 250 process ibm 250 tsmc ibm process gain 32k test asic fraction timing results single needed readout range dynamic calibration constant

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Slide1

Fabrication Process OptionsGary Varner

Specification Details are often Application SpecificIs IBM 130nm always the best choice?

1

6-OCT-2010 Electronics GPC ReviewSlide2

2

An example app: single g timing

Belle II imaging TOP

(PID upgrade)Slide3

3

Photo-detector: Hamamatsu SL-10Approximate 1” x 1”4 x 4 multi-anode

Interesting mechanical challenges (case at HV)Lifetime protectionSlide4

Gain Needed

What gain needed?At 10

6 gain, each p.e. = 160 fC

At 2

x

10

5

gain (better for aging), each p.e. = 32 fC

In typical ~5ns pulse, Vpeak = dQ/dt * R = 32uA * R = 32mV * R [k

W

] (6.4mV)

Amplifiers dominate board space

Readout ASIC pairSlide5

5

Highly integrated readout electronics

100mm high

147mm long

front-end moduleSlide6

6

SL-10 Timing Performance

Nagoya

Hawai’i

σ

~ 38.37

Nagoya = constant fraction discriminator + CAMAC ADC/TDC

Hawai’i = waveform sampling + feature extractionSlide7

Updated results – single g

7

 Relaxes needed bandwidth: 400-500 MHz looks adequateSlide8

8

ASIC options

ASIC

ABW [GHz]

Sampling [

Gsa

/s]

# of Channels

Amp G

[dB]

SCA

depth

Fab

vendor

Size [nm]

PSEC3

~2?

~10

4

0256IBM

130DRS4

~1~58Ext.

1kIBM250

BLAB3

~0.2

~4

8

27

32k

TSMC

250

BLAB3A

~0.7

~4

8

36

32k

TSMC

250

IRS

1.0

4/8

8/4

0

32k

TSMC

250

IRS2*

1.5

4/8/12/16/32

8/4/3/2/1

0

32k

TSMC

250

STURM2

~3

10-100

8

0

4x8

TSMC

250

TARGET2*

~0.5

0.5-2

16

30

16k

TSMC

250

TARGET2B*

1.0

0.5 - 4

16

0

16k

TSMC

250Slide9

9

About 1 submission every 3 monthsSlide10

10Slide11

11Slide12

12

Project about 1 submission every 3 monthsSlide13

13

About 1-2 submissions/month

foreseenSlide14

14

Discussion:Is IBM 130nm always best choice?

CERN is certainly committed to the process

Fewer

fab

options, process requirements fussier

Many more designs in the 0.25um process:

2.5V VDD vs. 1.2V

fA

vs.

pA

leakage currents

Other techniques to get same performance results? Do plan to submit further CSA design (later)Slide15

Backup Slides

Some background context…15Slide16

16

Example p PDFs at 3 GeV/c

e

-

e

+

40°

90°

120°Slide17

17

Buffered LABRADOR (BLAB1) ASIC10 real bits of dynamic range, single-shot

Target few $$/channelLow power

Measured Noise

1.45mV

1.8V dynamic range

-3dB ~300MHz

6GSa/s

150MHz sine wave -- Pre-calibrationSlide18

18

CFD Test ConditionsFermilab test beam (120 GeV/c proton)Laser test setup

Electronics calibration setup

Test beam data raw (left) and time walk corrected (right). Laser results comparable.Slide19

19

Constant Fraction AlgorithmRelatively simple, but still some knobs to tune…Between waveform points, is it better to use linear interpolation or something else (e.g., spline).Which fraction optimizes timing resolution?

6/11/2010

19

Nishimura - LAPPD Collaboration MeetingSlide20

20