A Designer’s Perspective on Timing Closure - PowerPoint Presentation

Slide1

A Designer’s Perspective on Timing Closure

Greg

FordSlide2

IntroductionTiming closure is a key component of all design flows.Integrated into nearly every step and process.Automation important given the complexity of timing analysis / results.Designers interact with timing closure in multiple ways.

Configuring large-scale optimization runs.

Individual problem work with fine-grain optimizations.

Discussion of multiple key

areas in

the flow related to timing closure, and how

designers

do and

do not

leverage solutions.

Floorplanning automation

Clock tree design

Data net buffering

Hold time fixingSlide3

Design FlowProcesses in the design flow can be divided up into 2 major categories.Bulk OptimizationPrecision OptimizationTiming closure is a continuous process though the flow.

Most designer time is spent working on complicated fails left behind by bulk optimization.

Floorplanning

Placement / Opt

Clock Planning

Clock Tree Build

Post Clock Opt

Timing Closure

Timing Closure

Routing

Post Route Opt

Timing Closure

Precision

BulkSlide4

Bulk OptimizationAutomated processes that are designed to work for majority of cases.Default configuration covers most cases.Configurable to cover >95% of cases.Configuration can include hundreds of settings.

Plus even more secret settings.

Most CPU time is spent on bulk optimization.

Algorithm efficiency very important.

Most designer time is spent reviewing results and trying different experiments.Slide5

Precision OptimizationSemi-automated processes run by designers, which are tailored to very specific problem cases.Limited configuration – the more precise the process, the less configuration.Algorithmic efficiency less important.Better to generate a good solution slowly than an average solution quickly.

Majority of designer time is spent interactively working with these processes.

Review bulk results, categorize fails, select appropriate precision opts, write scripts to run opts.Slide6

Floorplanning for ClosureAutomated floorplanning tools have come a long way.Be sure your tool’s goals are in line with the designer’s goals.Designer’s themselves may not be fully aware of their goals.

A good seed placement is better than an attempted perfect solution.Slide7

Balancing your ConstraintsWire length is an easy metric to target, but can result in increased routability issues if not properly balanced.Pure reduction of wire length can lead to abutted block pins.Globally a good choice.

Locally

unroutable.Slide8

Unintended ConsequencesAbutting memories “back to back” provides the most efficient use of without risk of blocking pins.With a “surrounding” decap strategy, as frequency increases, abutted memories can become hot spots.

Center of abutted memories is farthest from surrounding

decaps

.

Separate memories to allow just enough room for

decaps

.Slide9

Keep it SimpleDesigner floorplans are geometrically regular for a reason.Satisfies all design rule requirements.Easy to make adjustments by sliding groups.

Inevitably, a designer will need to make floorplan adjustments.

With a floorplan they do not understand, it is easier to start from scratch than pick apart a failed solution.

Packing algorithms can do a good job of keeping a floorplan solution simple.

OK

OK

NO

NO

NO

Horizontal Subgroup

Vertical SubgroupSlide10

Building Clock TreesMany different styles available.Picking the best option is just as important as the floorplan for closure.Traditional TreeStandard repowering to all sinks.

Easy to automate.

Structured Tree

High power drivers serve large clusters of sinks.

Hard to automate – requires

floorplanning decisions prior to clock insertion.

Hybrid TreeStructured upper tree – traditional repowering for leaf levels.Slide11

Clock Tree StructuresTraditional clock tree (non-uniform)Structured large driver clock tree (uniform)

Latency 304ps

Skew 60ps

Depth 5

levels

Latency 340ps

Skew 80ps

Depth 9-14

levelsSlide12

Fringe Benefits / RoutingHighly structured clock distribution is helpful to congestion / routability.Globally distributing a clock tree with trunk routes on upper layers, and high-power drivers leaves lower layers open for more local routing.Upper tree and lower tree are on different layers, reducing per-layer congestion overhead.Slide13

Data Net Repowering

Data net repowering is used across the entire flow, with many different variations.

Navigate complex blockage topologies.

Redirect paths around congested areas.

Fix up electrical violations.

Designer timing closure uses specialty buffering solutions; resist the urge to make your buffering solution general-purpose.Slide14

Buffering for Electrical FixupNet with a slew/transition failure over a blockage.Don’t rely on general purpose cell legalization.If buffer lands on blockage, nearest legal location may be doubling back on the pre-existing path.

Specialty buffering for blockage should internally examine blockage and select good placements.

1

2

?Slide15

Buffering for Noise/SILong net running next to other long nets has a coupling/SI violation.Don’t rely on incremental analysis of SI while buffering.Once the first buffer goes in on the net, wiring data will be invalidated and incremental SI data would be suspect.

Specialty buffering should use a spec driven approach to insert

a complete

buffering solution prior to a full route update and re-analysis.

1

2

3Slide16

Technology EvolutionBuffering solutions are highly tied to technology parameters.Some specialty opts from a prior technology may no longer apply when moving to a new technology.Moving from 32nm to 14nm processMetal stack continues to get “thinner” – reduced effectiveness of wide wires on same layer vs. higher layers in heterogeneous metal stack.

FinFETs

drive much more cap load per cell area – can quickly run into EM limits; selecting largest buffer available may waste area.Slide17

Adding ComplicationsDesigners can be their own worst enemy in terms of diluting precision optimizations via enhancement requests.“Can your process handle this new special situation that I have on my current design?”New problem statements are best served with new solutions.

Sometimes the best solution is a one-off process managed by the designer themselves.Slide18

Hold Padding

Hold padding is

an

area where current precision optimization does a good job.

Limited varieties of hold fails means that very specific algorithms are still able to handle most violations without sacrificing effectiveness for coverage.

Simplest case is a pure hold fail on a data pin.

Insert padding directly on failing pin until path is slowed down sufficiently to pass the hold check.Slide19

Contending Sub-pathsMost common complication in hold padding is breaking a setup path to the same capture pin.Short path and long path come together in logic cone.Well handled by optimization processes.Check both setup and hold at insertion point.

If contention, trace backwards along each sub-path with a negative hold slack and check again.



Slide20

Placement ConsiderationsMany of the placement complications discussed for buffering can be avoided for hold padding by inserting at sink pins.Minimal pin cap change to existing net.No need for pad to drive wire load.Exposure only in case where placement is brick-walled, and insertion location choices are limited.

High density

Short path

sinkSlide21

ConclusionBulk optimization should be as efficient as possible.Precision optimization should be as specific as possible.Important that the process always produces a solution.Resist the urge to over-generalize.Be careful in selecting optimization goals.

Designers may not always be able to

accurately enumerate

the goals that they

would manually

work towards.

The designer is usually right; but not always.Designers generally have a good reason for wanting to solve problems in a certain way.If there is a different/better

solution, be prepared to educate.Interactive education.Plenty of examples.