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Circuit Lower Bounds Circuit Lower Bounds

Circuit Lower Bounds - PowerPoint Presentation

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Circuit Lower Bounds - PPT Presentation

A combinatorial approach to P vs NP Shachar Lovett Computation Input Memory Program Code Program code is constant Input has variable length n Run time memory grow with input length ID: 550222

parity circuits bounds depth circuits parity depth bounds small poly size monotone compute circuit problems simple mod input computation log approximate exponential

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Presentation Transcript

Slide1

Circuit Lower BoundsA combinatorial approach to P vs NP

Shachar

LovettSlide2

Computation

Input

Memory

Program

Code

Program code is

constant

Input has

variable length (n)

Run time, memory – grow with input length

Efficient algorithms = run time, memory

poly(n)Slide3

P vs NPP = problems we can solve

= efficient algorithm to

find solution

NP = problems we want to solve

= efficient algorithm to verify solutionExamples: graph 3-coloring, satisfiability ,…Slide4

ChallengeHow can you prove that some computational problems require >> polynomial time?In particular, one in NP

Combinatorial approach:

circuits

Replace “uniform computation” by a more combinatorial object

Slide5

CircuitsComplex computation = iteration of many small

simple

computations

x

Y

Z

AND

AND

AND

OR

Majority(X,Y,Z)Slide6

CircuitsComplex computation = iteration of many small

simple

computations

Simple

= any complete basis (e.g. AND,OR,NOT)

x1x2

x

3

x

4

x

5

x

6

x

7

x

8

x

n

f(X

1

,…,

X

n

)Slide7

Algorithms vs circuits

Circuits are as powerful

*

as algorithms:

Problems with efficient (poly-time) algorithms also have poly-size circuitsRevised challenge: show poly-size circuits cannot solve all interesting computational problems

Input

Memory

Code

x

1

x

2

x

3

x

4

x

5

x

6

x

7

x

8

x

n

f(X

1

,…,

X

n

)Slide8

Lower boundsGoal: show poly-size circuits cannot solve NP

Can prove lower bounds for restricted circuit models

Monotone circuits

Bounded depth circuits

General technique: Approximate circuit by a nice mathematical model Show the

mathematical model cannot solve the problem (not even approximately)Slide9

Monotone circuitsMonotone circuits

: circuits with just

AND-OR

gates (no NOT gates)

Compute monotone functions (e.g clique)Can clique have poly-size

monotone circuits?[Razborov’85, Alon-Boppana’87]: No. Clique requires exponential size monotone circuitsSlide10

Monotone circuits

x

1

x

2

x3x4

x

5

x

6

x

7

x

8

x

n

f(X

1

,…,

X

n

)

Input: n edges of

graph G

on m

n

1/2

vertices

Output: does G have large clique?

Circuit: poly-size with

AND-OR

gates

Step 1: approximate

AND-OR

circuit by

lattice

Step 2: show

lattice

cannot approximate cliqueSlide11

Bounded depth circuits

x

1

x

2

x3x4

x

5

x

6

x

7

x

8

x

n

f(X

1

,…,

X

n

)

Small

depth

= parallel computation

Efficient algorithms =

poly(n) depth

Can prove lower bounds for

depth << log(n

)

depthSlide12

Lower bounds for AND-OR-NOT circuitsParity(x

1

,…,

xn

) = sum of bits modulo 2Computed by small AND-OR-NOT circuits of depth log(n)Can the depth be reduced, while maintaining small size?

[Ajtai’83, Furst-Saxe-Sipser’84]: No. small (sub-exponential) AND-OR-NOT circuits of depth <<log(n) cannot compute parity[Yao’85, Hastad’86]: not even approximatelySlide13

Lower bounds for AND-OR-NOT circuitsMain idea:

random restrictions

of input

set

most inputs bits to random 0,1 values; leave remaining variables “alive”Simple computations: AND, OR, NOTGates with many inputs are

fixed by random restrictionIterate to make entire circuit simple (decision tree)Parity doesn’t simplify (becomes parity of fewer inputs)

X

1

AND

X

n

…Slide14

Lower bounds for AND-OR-NOT-PARITY circuitsWhat if we also allow parity gates as simple computations?

MOD

3

(x

1,…,xn) = sum of bits modulo 3Intuition: parities shouldn’t help compute MOD3[Razborov’87, Smolensky’87]: small (sub-exponential)

AND-OR-NOT-PARITY circuits of depth <<log(n) cannot compute MOD3Slide15

Lower bounds for AND-OR-NOT-PARITY circuitsLocal computation:

AND, OR, NOT, PARITY

Random restrictions fail: don’t simplify parity

Can approximate local computations by

low-degree polynomials modulo 2 (and by composition, approximate the entire circuit)Low degree polynomials modulo 2 cannot compute MOD3Slide16

Lower bounds for AND-OR-NOT-PARITY-MOD3 circuits

What if we allow both

PARITY

and

MOD3 gates as simple computation?Conjecture: cannot compute MOD5

in small size and depth <<log(n)[Williams’10]: cannot compute all NEXP - exponential analog of NP (problems whose solution can be verified in exponential time)