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Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device

Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device - PowerPoint Presentation

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Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device - PPT Presentation

State and explain the principles involved in attaining good mask alignment Identify and explain the various issues involved with designing good process flows Typical process steps for surface ID: 751941

alignment mask etch process mask alignment process etch flow wafer mark strip issues marks good layout design diffusion oxide

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Slide1

Process flow part 2

Develop a basic-level process flow for creating a simple MEMS device

State and explain the principles involved in attaining good mask alignment

Identify

and explain

the various issues involved with designing

good process

flowsSlide2

Typical process steps for surface

micromachining

This is where process flow becomes complicated.

modeling and simulation

design a layout

design a mask set

thin film formation (by growth or deposition)

lithography

etching

release

packaging

die separation

1

2

3

4

mask setSlide3

Mask design and layout

The

complete design with all mask layers combined is called the

layout

of the

device. Typically use software specifically designed for masks

Program allows you to place mask layers on top of each other to ensure good alignmentEach mask layer shown in a different color and/or line styleThe software will separate the layers into the individual masks for fabrication. The software also keeps track of whether masks should be positive or negative depending on whether the process is typically additive or subtractive

Mask layoutSlide4

Mask design and layout

Every

mask

must

have alignment marks that will align the mask to the features on the wafer.

Mask

alignment

mask aligned with wafer

alignment feature on wafer

alignment feature on maskSlide5

Mask design and layout

Issues

to think about when designing the shape and the placement of the alignment mark:

Does the

alignment mark shape give wafer orientation as well as alignment

?

Asymmetry is good

 a cross is better than a “plus”A circular mask opening will produce a square etch in Si showing crystal directions. Align next masks to the squareMake sure your mask does not obscure your alignment mark!You must be able to see the entire alignment mark through

your mask Dark areas on masks very dark in order to keep light from going through

Features on a wafer tend to be grayIt is good to leave a little “wiggle room” around alignment mark on the wafer

Mask alignmentSlide6

Mask design and layout

Use

a variety of alignment

marks

Use one large alignment mark one

to get a sense of where you are on the

waferUse smaller ones to fine tune the

alignmentUse several marks on opposite sides of the wafer. A small error in angle can propagate into a large error across the distance of the wafer Be sure your alignment mark is in a material you can see.You can see edges in most structural materials and in metalsYou

cannot see diffusion!If your first step in the process flow is diffusion, you may need to add another mask to create an alignment mark. Otherwise

, you may place the first alignment mark in the first mask you use First patterning  first alignment markMask alignment

TT

TTSlide7

Mask design and layout

Know

the process flow

of your alignment marks

The

process flow

of the alignment marks may be different than that of the whole device since the alignment marks see every mask layer and most of your

structural/sacrificial layers do notDoes a process step obscure or eliminate an alignment mark you intended to use? (E.g., does a deposited layer covers it up?) If so, you must create another one.Backside alignmentBackside alignment requires a special “backside aligner” that uses lasers and/or mirror to find the alignment mark on the backside of the wafer.Mask

alignmentSlide8

Surface μ

-machined pressure sensor

Silicon substrate

Poly-Si diaphragm forms one plate of capacitor.

n+ diffusion layer forms other “plate” of capacitor

  

Aluminum wires send

capacitive

electrical signal off the chip

.

Oxide layer insulates aluminum wires from rest of chip

 

Nitride insulates poly-Si diaphragm from n+ diffusion.

Notches to prevent

uncompensated stresses from breaking diaphragm during releaseSlide9

Process flow, pass 1

We can go through this example a little quicker.

What are the

major steps to create the device?

  

Diffusion of n

+

dopant for bottom “plate” of capacitorDeposit nitride for electrical insulationDeposit sacrificial oxideAdd poly-Si diaphragmNeed pedestals andnotches to form diaphragmSacrificial etchCreate wires

C

But isn’t release supposed to be last?Slide10

Detailed process flow

Mask 2

Diffusion of n+ dopant for bottom “plate” of

capacitor

Note

that since we cannot see diffusion we will need to etch alignment marks in the wafer first

.

Mask 2 – what does it look like? (Assume positive resist.)

Breakdown of this step:Etch alignment marks into waferPhotolithography so that ion implantation only goes

where you want it to go Ion implantationRemove photoresist

Drive-in Deposit nitrideNo

mask is required since it covers the entire waferMask 2

Mask 1 is for alignment marksSlide11

Detailed process flow

Mask 3

Deposit sacrificial oxide

No mask is required since it covers the entire wafer

Why cover the whole wafer? Why not pattern oxide to go just under the diaphragm and nowhere else

?

Add

poly-Si diaphragmHow do we produce notches and pedestals?

We will need two different etches.What will our etch stop method be?  Timed etch

Breakdown of this step:Photolithography notches (Mask?)

Etch notchesPhotolithography pedestals (Mask?)Etch

pedestalsDeposit poly-SiPhotolithography poly-Si (Mask?)

Etch poly

Mask 3

Mask 4

Mask 5

Mask 4

Mask 5Slide12

Detailed process flow

Sacrificial etch

If

using oxide for both sacrificial layer and insulation for the wires, need to do sacrificial etch

before

laying the oxide for the

wires. Why?

Contact lithography requires release to be done last. Why? How would we change our process flow if we have to do contact lithography?Create wiresDeposit

oxidePhotolith contact cuts (mask?)

Etch contact cutsDeposit AlPhotolith

Al (mask?)Etch Al

Mask 6

Mask 6

The height of the features is exaggerated, but the importance of the “depth of focus” idea is very

clear

.

Mask 7

Mask 7Slide13

Final process flow

Final Process Flow for

Surface

Micromachined

Pressure

Sensor

Starting material: 100mm (100) p-type silicon, 1×1015

cm-3 boron with a 10 mm n-type epilayer, 5×1016 cm-3 phosphorus

Clean: Standard RCA cleans with HF dipPhotolithography: Mask 1 (alignment)Etch: Etch alignment marks into Silicon.

Strip: Strip photoresistPhotolithography: Mask 2 (n+ diffusion)

Implant: Ion implantation of phosphorousStrip: Strip photoresistClean: RCA cleans, no HF dip

Drive-in: Drive in diffusionClean: RCA cleans, no HF dipNitride: Deposit insulating nitride layerOxide:

Deposit sacrificial SiO2Photolithography: Mask 3 (notches)Etch: Short etch to get notches

Strip: Strip photoresistPhotolithography: Mask 4 (pedestals)Etch: Longer etch to get pedestals

Strip: Strip photoresistClean: RCA cleans, no HF dipPolysilicon: Deposit

polysilicon for diaphragmPhotolithography: Mask 5 (diaphragm)Etch: Etch polysilicon

Strip: Strip photoresistSacrificial etch: Remove oxide leaving pedestalClean: RCA cleans, no HF dip

Oxide: Deposit SiO2 for insulationPhotolithography: Mask 6 (vias)Etch: Etch oxide to get vias

Strip: Strip photoresistClean:

RCA cleans, no HF dipMetal: Deposit aluminum

for wiresPhotolithography:

Mask 7

Etch:

Etch AluminumStrip: Strip

photoresistSinter: Anneal contactsSlide14

Other issues in process flow

Other issues in designing good process flows

System partitioning

:

Whether

or not to integrate the

MEMS device

and any necessary electronics on the same chipIntegration limits MEMS process steps due to temperature, materials, etc.Process partitioning: Material used in one process bond with and/or affect the properties of materials in another processes? If so, the order of the process steps

may matter significantly.Backside processingMakes many fabrication processes easier, but alignment is more difficultAlso must take into account which steps affect both sides of wafer and which ones affect only one side

Thermal constraintsE.g., photoresist cannot withstand high temperatures, High temperatures further drive-in dopantsSlide15

Device geometry

Hard to visualize the 2-D and 3-D aspects of devices 

Solid-modeling, CAD software

developed specifically for

MEMS

Combination of conformal deposited layers with directional etching can result in

stringers

Can use

planarization to avoid stringers, depth of focus problems, and other issues arising from large changes in topography

Other issues in process flow

Other issues in designing good process flows

An example of a “floating stringer” (Courtesy of Sandia National Laboratory

stringerSlide16

Other issues in process flow

Other issues in designing good process flows

Mechanical stability

:

Fabrication can result in the formation of different

stresses

in structural layers, causing them to bend or break

Process accuracy: Expansion or shrinkage of photoresistVariations in the thickness of layersPresence of photoresist in structural layersMask misalignment between layersDesign rulesC

Coming up next!Slide17

Other issues in process flow

If using a wet etchant in step 7

isotropic or anisotropic

C

Undercutting

C

A MEMS wheel and hubSlide18

A win-win process flow

The self-aligned gate transistor

metal electrode

overlap causes unwanted increase in capacitance, slower switching speed

n

+

doping

p type wafer

poly Si electrode

use poly as electrode

and

as mask for doping

virtually no gap increases

in

switching speed significantly