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Search Results for 'dram chip'
dram chip published presentations and documents on DocSlides.
Gather-Scatter DRAM In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided
by helene
Vivek Seshadri. Thomas Mullins, . Amirali. . Boro...
Gather-Scatter DRAM
by marina-yarberry
In-DRAM Address Translation to Improve the Spatia...
Scalable Many-Core Memory Systems Topic 1: DRAM Basics and
by tatyana-admore
DRAM Scaling. Prof. Onur Mutlu. http://www.ece.cm...
Language-Directed Hardware Design
by calandra-battersby
Language-Directed Hardware Design for Network Per...
3D Systems with On-Chip DRAM for Enabling
by ellena-manuel
Low-Power High-Performance Computing. Jie. Meng,...
Threats and Challenges in FPGA Security
by alexa-scheidler
Ted Huffmire. Naval Postgraduate School. December...
A Cache-Like Memory Organization
by ellena-manuel
for 3D memory systems. CAMEO. 12/15/2014 MICRO. C...
Cooperative Cache Scrubbing
by natalia-silvester
Jennifer B. Sartor, . Wim. . Heirman. , Steve Bl...
Hardware Support for Trustworthy Systems
by min-jolicoeur
Ted . Huffmire. ACACES 2012. Fiuggi. , Italy. Dis...
A Case for Refresh Pausing in DRAM Memory Systems
by phoebe-click
Prashant. Nair. Chia-Chen Chou . Moinuddin Qure...
A Case for Refresh Pausing in DRAM Memory Systems
by pasty-toler
Prashant. Nair. Chia-Chen Chou . Moinuddin Qure...
Flipping Bits in Memory Without Accessing Them:
by lindy-dunigan
DRAM Disturbance Errors. Yoongu Kim. Ross Daly, J...
CS 152 Computer Architecture and Engineering
by tatiana-dople
Lecture 6 - Memory. Dr. George Michelogiannakis....
Addressing Prolonged Restore Challenges in Further Scaling DRAMs
by phoebe-click
Xianwei Zhang. Youtao. Zhang (advisor). CS, Pitt...
Computer Architecture Prof.
by natalia-silvester
Dr. . Nizamettin AYDIN. naydin. @. yildiz. .edu.t...
CS 152 Computer Architecture and Engineering
by olivia-moreira
Lecture 6 - Memory. Dr. George Michelogiannakis....
Computer Architecture: Main Memory (Part I)
by eddey
Prof. Onur Mutlu. Carnegie Mellon University. Main...
RowClone Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization
by delilah
Y. Kim, C. . Fallin. ,. D.. Lee, . R. . Ausavaru...
Engin Ipek 1 , Onur Mutlu
by olivia-moreira
1. , Jose F. Martinez. 2. , Rich Caruana. 2. Self...
F AULT
by mitsue-stanley
S. IM. : A Fast,. Configurable . Memory-Reliabil...
CACTI-IO: CACTI With
by danika-pritchard
Off-Chip Power-Area-Timing Models. Norman P. . Jo...
Tracking Millions of Flows
by test
In . High . Speed Networks . for . Application Id...
Computer Organization
by mitsue-stanley
. and Architecture. William Stallings . 8th Edi...
Hardware-Software Co-Design for
by giovanna-bartolotta
Network Performance Measurement. Srinivas Narayan...
Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers
by marina-yarberry
Manu Awasthi , . David Nellans. , Kshitij Sudan, ...
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories
by aaron
CACTI 7: New Tools for Interconnect Exploration i...
INTERNAL MEMORY (Part 1)
by celsa-spraggs
Semiconductor Main . Memory. Nowadays, the . use ...
ECE 552 / CPS 550 Advanced Computer Architecture I
by aaron
Lecture 12. Memory – Part 1. Benjamin Lee. Elec...
Enabling Technologies for Memory
by test
Compression. : Metadata, Mapping and Prediction. ...
Qiuling
by celsa-spraggs
Zhu, . Navjot. . Garg. , Yun-Ta Tsai, Kari . Pu...
Cosmic Rays Don’t Strike Twice:
by alida-meadow
Understanding the Nature of DRAM Errors and the I...
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