Koo smkoo1989gmailcom NVM Duet Unified Working Memory and Persistent Store Architecture Ren Shuo Liu DeYu Shen ChiaLin Yang Shun Chih Yu ChengYuan Michael Wang Index Background ID: 613619
Download Presentation The PPT/PDF document "Sungmin" is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
Slide1
Sungmin Koosm.koo1989@gmail.com
“NVM Duet: Unified Working Memory and Persistent Store Architecture”
Ren-
Shuo
Liu, De-Yu Shen, Chia-Lin Yang, Shun-
Chih
Yu, Cheng-Yuan Michael WangSlide2
IndexBackgroundIntroductionData Consistency vs. Bank-Level
ParallelismData Durability vs. Write SpeedNVM DuetEvaluationSlide3
Background
Structure of PCM(Phase Chang Memory) cell
2-states
Amorphous state(high resistance, 0)
Polycrystalline state(low resistance, 1)
Read and Write mechanisms of PCM
RESET(writing bit “0”)
Heat the phase change material
Short latency
High power consumption
SET(writing bit “1”)
Sustained low voltage pulse
Long latency
Low power consumption
To read
the state
of phase change material, a low enough
voltage pulse
is applied to the material.Slide4
Background
MLC PCM
The large resistance difference between the
amorphous state
and the polycrystalline state makes it
possible to
store multiple bits per PCM
cell
‘Iterative programming’
techniqueSlide5
BackgroundCharacteristics Comparison
PCM memory system architecturesSlide6
IntroductionNVM technologies have gained
a lot of attention recently.Non-volatile, byte-addressabilitySCM blurs the line between working memory and persistent store
.
E
nable
the
construction of
large-scale working
memory
High density, scalability, MLC technique
Alternative to conventional persistent store.can be connected to CPUs via a direct memory
access path
Ordinary load, store instruction(previous study)
SCM will play the role of both working memory and persistent store at the same time.
NVM duet
Guarantee
consistency
and
durability
not require advance partitioning of PCM resources
between persistent
store and working
memory
A
ll
the
management is
transparent to applications
.Slide7
Data Consistency vs. Bank-Level ParallelismAchieve consistency mechanism
Persistent update mechanisms at the software levelJournaling, shadow updateE
nforcing
ordering writes
at the hardware
level
Consistent update
I
ssues
write
requests to
create N3’ and
N4’
Issuing write requests
to create N1’, which points to N2, N3’, and N4
’
Issue a barrierSlide8
Data Consistency vs. Bank-Level Parallelism
Figure 3(a) displays a schedule that respects the barriers.
Figure
3(
b
) shows
if the barriers were not present
.
Figure
3(c) have
knowledge of the use case for each writeA, B, and G belong to working memoryThe others
belong to persistent storeSlide9
Data Durability vs. Write Speed
The write speed can be estimated based on the target band allocationA small
R
is used for a narrow target band to
prevent the
iterative write from completely missing the target band.
Resistance drift
PCM’s limited non-volatility
The resistance of PCM cells drifts upward
Occur data lossesSlide10
NVM
Duet
HW/SW Interface
Built on recently proposed software framework(NV-heap, Mnemosyne)
P
rogrammers declare persistent
data in the PCM main
memory(keywords)
L
ink
persistent data to a reserved virtual address space (PersistSpace)
AllocMap
(one bit each PCM frame)
C
onvey
to the memory controller the OS’s
knowledge of
the use case of each piece of dataSlide11
NVM DuetDuet Schedulerfully exploit the bank-level
parallelismRule 1: Writes to working memory can be scheduled regardless of barriers.Rule
2: Writes to persistent store are prioritized over
writes to
working memory if a barrier is pending in the
memory controller
.Slide12
NVM DuetDual-Retention PCM ArchitectureDual-Retention PCM chips
Provide two access modes with different retention guaranteesCommand interface(mode signal)
Smart Refresh
Remove unnecessary refreshing operationSlide13
EvaluationSlide14
EvaluationSlide15
ReferencesHaros Volos, Andres Jaan
Tack, and Michael M.Swift. Mnemosyne: Lightweight Persistent Memory
.
Ju
-Young Jung and
Sangyeun
Cho.
Memorage
: Emerging Persistent RAM based Malleable Main
Memory
and Storage Architecture.유승훈,
이은지
,
반효경
.
Design
and Implementation of a Write Efficient Journaling File System for Phase Change
Memory.
Eunji Lee,
Hyokyung
Bahn
, and Sam H. Noh.
Unioning of the Buffer Cache and Journaling
Layers with
Non-volatile
Memory.
Fei
Xia,
Jin
Xiong, and Ning-Hui Sun. A survey of Phase Change Memory System.Slide16
Q&A