1 COMP541 - PowerPoint Presentation

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COMP541Memories - I

Montek Singh

Oct 7, 2015Slide2

TopicsOverview of Memory TypesRead-Only Memory (ROM): PROMs, FLASH, etc.Random-Access Memory (RAM)Static todayDynamic next

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Types of MemoryMany dimensionsRead Only vs. Read/Write (or write seldom)Volatile vs. Non-VolatileRequires refresh or notLook at ROM first to examine interface

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Non-Volatile Memory TechnologiesMask (old)  ROMread-only memoryFuses (old)  PROMprogrammable read-only memoryErasable  EPROMerasable programmable read-only memoryElectrically erasable  EEPROM

electrically-erasable programmable read-only memorytoday called FLASH!used everywhere!

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Details of ROMMemory that is permanentk address lines2k itemsn bits

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Notional View of InternalsMain components:decoder for address decoding  select one row“wired-OR” per bit  OR’s together mintermsORing done by connecting outputs of effectively tristate buffers

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Programmed Truth Table

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ROM after programmingRemember:OR is a “wired OR”output is 1 if any of the rows with an intact fuse is 10 otherwise

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Mask ROMsOldest technologyOriginally “mask” used as last step in manufacturingSpecify metal layer (connections)Used for volume applicationsLong turnaroundUsed for applications such as embedded systems and, in the old days, boot ROMbut cheap to mass produce!

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Programmable ROM (PROM)Early ones had fusible linksHigh voltage would blow out linksFast to programSingle use

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UV EPROMErasable PROMCommon technologies used UV light to erase complete deviceTook about 10 minutesHolds state as charge in very well insulated areas of the chipNonvolatile for several (10?) years

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EEPROMElectrically Erasable PROMSimilar technology to UV EPROMErased in blocks by higher voltageProgramming is slower than readingToday’s flavor is called “flash memory”Digital cameras, MP3 players, BIOSLimited lifeSome support individual word write, some blockOur boards have it:A flash memory chip on our Nexys boardsHas a “boot block” that is carefully protectedWe will learn to use it in upcoming labs

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How Flash WorksSpecial transistor with floating gateThis is part of device surrounded by insulationSo charge placed there can stay for yearsAside: some newer devices store multiple bits of info in a cellInterested in this?Let’s cover briefly

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FlashAdd an extra gate to an nMOS transistora “float gate” below the actual control gatefloat gate is isolated from everything elsecan hold electrons for a whilecharge on float gate determines bit value storedelectrons deposited  negative charge does not allowtransistor to turn onif no electrons on float gate  transistor can be turned on by the control gate14

https://en.wikipedia.org/wiki/Flash_memorySlide15

FlashAdd an extra gate to an nMOS transistorcharge on float gate determines bit value storedfloat gate can be cleared using high voltageerased  ‘1’ valuecannot erase individual bits: must clear an entire “block” or “page”can write individual bitsfor fast write speeds:must have empty blocks availablespeeds slows down as memory fillsthus, garbage collection is important overprovisioning used in SSDs15

https://en.wikipedia.org/wiki/Flash_memorySlide16

Read/Write MemoriesFlash is obviously writeableBut not meant to be written rapidly (say at CPU rates)And often writing needs erasure of entire blocksFor frequent writing, use RAM

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Random Access MemoriesSo called because it takes same amount of time to address any particular locationNot entirely true for modern DRAMs, but somewhat true…First look at asynchronous static RAMreading and writing typically controlled by “handshakes”clock may still be present, but actions controlled by handshake signals

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Simple View of RAMTypical parameters:some word size nsome capacity 2kk bits of address lineNeed a line to specify reading or writingtypically only one wire neededsometimes two separate ones

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Example: 1K x 16 memoryRAM comes in variety of sizesfrom 1-bit widemain issue is no. of pins available on chipMemory size often specified in bytesThis would be 2KB memory10 address lines (=1K locations)16 data lines (=2 bytes/location)

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WritingSequence of stepsSet up address linesSet up data linesActivate write line (e.g., maybe a positive edge)

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ReadingStepsSetup address linesActivate read lineData available soonfor asynchronous memory: after simply a specified amount of timefor synchronous memory: after a clock edge

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Chip SelectEnable:Usually a line to enable the chipWhy?

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Timing: Writing

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Timing: Reading

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Static vs. Dynamic RAMDifferent internal implementations: SRAM vs. DRAMDRAM:DRAM stores charge in capacitorDisappears after short period of timeMust be refreshedSmall sizeHigher storage density  larger capacitiesSRAM:SRAM easier to useUses transistors (think of it as latch)FasterMore expensive per bit

Smaller sizes

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Structure of SRAMInternally, each bit stored in a “latch”One memory cell per bitCell consists of a few transistorsNot really a latch made of NANDs/NORs, but logically equivalentBehaves like an SR latchControl logicalso need extra logic around the latch to make it work like a memory cell

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Structure of SRAMSeveral optimized circuits often usedreplace a full-fledged SR latch with something simpler, smaller, faster…Not really a latch made of NANDs/NORs, but logically equivalentBehaves like an SR latche.g., a simpler 6-transistor memory cellwordline  Select(bitline, bitline’)  (B, B’) as well as (C, C’)

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Example: A Simple OrganizationNote:In reality, more complexOnly one word-line is “on” at a time

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Zoom in: A single bit sliceOperation:Cells connected to form 1 bit position (column)Word Select enables one latch from address linesonly this cell is writableonly this cell is readB (and B’) set by:Read/Write’Data InBit Select

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Let’s look at a single bit cell

Example:

0

1

Z

Z

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Bit Slices and ModulesEntire column of cells

called a bit slice

basically a 1-bit wide memory!

Module

module refers to a single chip of memory

1-bit wide memory chips are quite common!Slide32

Inside an SRAM Bit CellActual implementation does not use a real SR latch!a tinier approximation is usedlogically behaves very much like an SR latchbut much smaller and faster!

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16 X 1 RAM “Chip”

Now shows

address decoder

selects appropriate locationSlide34

Row/Column LayoutFor larger RAMs:decoder becomes pretty bigalso run into chip layout issuesTypically:larger memories use “2D” matrix layoutsee next slide

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16 X 1 RAM as 4 X 4 Array

Two decoders

Row

Column

Address just broken up

Not visible from outside on SRAMsSlide36

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Not the same as 8

X 2

RAM!

Minor change in

logic and pins

Spot the difference!Slide37

Spot the difference!

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Realistic SizesExample: 256Kb memory organized 32K X 8Single-column layout would need 15-bit decoder with 32K outputs!Better organization:A 2D (i.e., square) layout with:9-bit row and 6-bit column decoders

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SRAM PerformanceLatency and Throughput importantCurrent ones have cycle times in low nanosecondssay 1-2ns (top-end ones even lower)Used as cache (typically on-chip or off-chip secondary cache)Sizes up to 8Mbit or so for fast chipsExpensive ones can go a bit biggerEnergy/powerSRAMs also better for low

power vs. DRAMs

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Wider MemoryWhat if you don’t have enough bit width?use multiple chips and side-by-side40Slide41

Larger/Wider MemoriesMade up from sets of chipsConsider a 64K by 8 RAMour building block

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LargerLet’s build a larger memory256K X 8Decoder for high-order 2 bitsSelects chipLook at selection logicAddress rangesTri-state outputs42Slide43

SummaryToday we looked at:Quick look at non-volatile memoryStatic RAMNext topic:Dynamic RAMComplex, largest, cheapMuch more design effort to useTalk about memories for lab43