Keren Zhu Hao Chen Mingjie Liu Xiyuan Tang Nan Sun and David Z Pan ECE Department The University of Texas at Austin This work is supported in part by the NSF under Grant No 1704758 and the DARPA ERI IDEA program ID: 1035683
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1. Effective Analog/Mixed-Signal Circuit Placement Considering System Signal FlowKeren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun and David Z. PanECE DepartmentThe University of Texas at AustinThis work is supported in part by the NSF under Grant No. 1704758, and the DARPA ERI IDEA program
2. Speaker – Keren ZhuKeren Zhu is a Ph.D. student at ECE Department at UT Austin under supervision of Prof. David Z. Pan.Keren Zhu’s research interests include general topics in VLSI physical design with a focus on analog layout automation.
3. Background: Automating AMS LayoutsThere are high demand for analog and mixed signal (AMS) circuitsDrawing AMS layouts are still manual and cost timeSources: IBMAdvanced computingHealthcareCommunication
4. Background: MAGICALThis work is part of MAGICAL Machine Generated Analog IC Layout https://github.com/magical-eda/MAGICALPlacer codesBenchmark netlists (sanitized)
5. Motivation: placer v1Placer v1. [Xu+ ISPD19]First version of MAGICAL placer prototypeAbstracted problem formulationNot really consider performance yetNLP+LPB. Xu, S. Li, C.-W. Pui, D. Liu, L. Shen, Y. Lin, N, Sun and D. Z. Pan, "Device Layer-Aware Analytical Placement for Analog Circuits," ISPD’19
6. Motivation: router v1Placer v1. [Xu+ ISPD19]First version of MAGICAL routerLVS correctStart working on optimizing performance with simulation resultsOTA/Comparator benchmarksRouter v1. [Zhu+ ICCAD20]K. Zhu, M. Liu, Y. Lin, B. Xu, S. Li, X. Tang, N. Sun and D. Z. Pan, ”GeniusRoute: A New Routing Paradigm using Generative Neural Network," ICCAD’19
7. Motivation: hierarchical flowPlacer v1. [Xu+ ISPD19]MAGICAL start working on ADCAutomatically tuning parameters for building block-level performanceManual tuning on top-level placementRouter v1. [Zhu+ ICCAD19]Hierarchical flow [Liu+ DAC20]M. Liu, K. Zhu, X. Tang, B. Xu, W. Shi, N. Sun and D. Z. Pan, ”Closing the Design Loop: Bayesian Optimization Assited Hierarchical Analog Layout Synthesis," DAC’20
8. Problem 1: system signal flowManual tuned in DAC20
9. Problem 2: sensitive building block performancePlacer is not robustSensitive to the initial condition and parametersGood results need some luckNumerical optimization need to be improvedIR drop is an issuePlacer should consider more in planning power routing
10. Motivation: placer v2Placer v1 [Xu+ ISPD19]Router v1 [Zhu+ ICCAD19]Hierarchical flow [Liu+ DAC20]Placer v2 [Zhu+ ICCAD20]This work
11. Motivation: router v2Placer v1 [Xu+ ISPD19]Router v1 [Zhu+ ICCAD19]Hierarchical flow [Liu+ DAC20]Placer v2 [Zhu+ ICCAD20]This workRouter v2 [Chen+ ICCAD20]2A.3 Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits
12. Motivation: router v2Placer v1 [Xu+ ISPD19]Router v1 [Zhu+ ICCAD19]Hierarchical flow [Liu+ DAC20]Placer v2 [Zhu+ ICCAD20]This workRouter v2 [Chen+ ICCAD20]2A.3 Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits
13. Placer v2 contributions in high-level viewMagical placer v2 has:Building Block LevelSystem LevelNew System Signal Flow CostSelf-adaptive multiplier updatesGradient-based NLP optimizationNew Power Net WL model
14. Placer v2 flowGlobal placement decides the rough locations of each blocksIterative numerically solve non-linear optimization problemIncrease penalty multipliers for overlapping, etc. in each iterationLegalization ensure spacing and symmetryConstraint graph + Linear programming
15. System signal flow cost formulationWant straight signal flow
16. System signal flow cost formulationMinimize the angle θ
17. Fit more accurate power WL modelPin-to-stripe power routingDisclaimer: this WL model is targeting for MAGICAL router v2
18. Better multiplier updating schemeFor better numerical robustnessMatching initial gradient normEncourage comparable efforts to different costsSubgradient method to increase penaltyUse WL as common referenceIncrease penalty based on how much is the violations
19. Gradient-based optimizationAdam optimizer for general casesVanilla gradient descant when convergence is slowDisclaimer: not well tuned. Adam with lower step size itself might also worksHow to update multipliers is in general more important than optimization kernels
20. LegalizationGenerate a relational constraints and use linear programming to solve the compactionSimilar to [Xu+ ISPD’19]
21. Experimental results on two ADCsSystem signal flow boosts the performance for two CTDSM ADCsCircuitsSchematicWithout SSFWith SSFADC1SNDR (dB)66.261.463.6SFDR (dB)76.975.077.1THD (dB)75.070.673.8ENOB (bits)10.709.9010.27Power (mW)0.8370.8640.870ADC2SNDR (dB)67.159.666.3SFDR (dB)82.067.080.2THD (dB)77.666.576.4ENOB (bits)10.859.6110.71Power (mW)0.6770.7400.757
22. Experimental results on block-level circuitsOutperform [Xu+ ISPD19] in bothWL and areaMore details in the paperCKTsISPD’ 19This WorkAreaHPWLRWLVIAAreaHPWLRWLVIACOMP2231042672118710119613OP12366767123497158469190584OP2252941691444204746673250
23. The ADC2 chipThe ADC2 core using the proposed placer has been taped-out and verified in measurementsADC2
24. ConclusionSystem signal flow is effective for two CTDSM-ADCsConfirm with designers that this is a general approach for a broader range of circuit classesBetter numerical optimization is effective in NLP global placementFitting WL model to the target model is effectiveImportant for nets with special routing strategyFuture works:Placement and routing techniques for specific circuit classesAdvance technology nodesE.g. FinFET technology