Verification Environment for a Simple Pixel Chip Model - PowerPoint Presentation

Slide1

Verification Environment for a Simple Pixel Chip Model

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

1

E.

Conti

*

,

P.

Placidi

*

, S. Marconi

*, +

, J. Christiansen

+

* DIEI

– University and INFN Perugia

(Italy

)

+

CERN

elia.conti@

diei.unipg.itSlide2

Goals

Activity

performed in

RD53

(

workpackage WG3: “Simulation Testbench”) RequirementsDefinition and evaluation of requirements for next generation pixel chipsSystem performance evaluation for different pixel architecturesPixel architecture optimization based on pixel grouping (validation of statistical study)

2

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

Devoted

simulation and verification frameworkSlide3

Verification Environment – Current Version

SystemVerilog

class-based verification environment

Automated hit generation (random and from file)

Conformity checks between pixel chip inputs and outputs

Monitoring of lost hitsReporting on lost hits (why hits are lost)3Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013Slide4

Verification Environment – DUT (1)

4

Pixel chip contains a single Pixel Region (PR) with a

parametrised

number of Pixel Unit Cells (PUC)

PR buffer is an array of SystemVerilog queuesPixel Phase 2 Electronics Meeting during TK Week – 27-08-2013PIXEL CHIP

PIXEL REGION (PR)

END OF COLUMN

PIXEL MATRIX

PR BUFFER

TRIGGER

LOGIC

ToA

ToT

HIT PACKETS

TIME TAG

HITS

TRIGGER

Digital

PUC

ToT

c

onv.

.....

.....

.....

PIXEL BUSY FLAGS

PR BUFFER FULL FLAGSlide5

Verification Environment – DUT (2)

5

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

In order to keep hit generation as general as possible a simple

ToT

converter module has been defined which abstracts the behavior of the analog front-endPIXEL UNIT CELL

Digital

PUC

ToT

converter

ANALOG HITS

DISCRIMINATOR

OUTPUTS

ToA

ToT

PIXEL BUSY FLAGSSlide6

Verification Environment – DUT (3)

6

Pixel Phase 2 Electronics Meeting during TK Week

– 27-08-2013

Pixel chip contains a single Pixel Region (PR) with a

parametrised number of Pixel Unit Cells (PUC)PR buffer is an array of SystemVerilog queuesPIXEL CHIP

PIXEL REGION (PR)

END OF COLUMN

PIXEL MATRIX

PR BUFFER

TRIGGER

LOGIC

ToA

ToT

HIT PACKETS

TIME TAG

HITS

TRIGGER

Digital

PUC

ToT

c

onv.

.....

.....

.....

PIXEL BUSY FLAGS

PR BUFFER FULL FLAGSlide7

Verification Environment – Block Diagram

7

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

DUT

PixelChip

PixelChip Interfaces

(hit_intf, trigger_intf, readout_intf, flag_intf)

PixelChipHarness

Clock and reset

generator

PixelChipEnv

Stimuli_Component

HiLevel_Generator

Hit_Driver

Analog hits

Hit_Monitor

Readout_Component

Readout_Monitor

Trigger_Driver

HiLevel_Trans

Flag_Component

Flag_Monitor

CONFORMITY

CHECKER

Flag_Trans

Trigger_Monitor

Trigger_Time_Trans

Hit_Time_Trans

Readout_Trans

Hit_Generator

HiLevel_Trans

Hit_TransSlide8

Verification Environment – Components (1)

8

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

Component

-

instance_name

: string

-parent : Component

#children[$] : Component

+new(_

instance_name

: string, _parent : Component)

+

body()

+

get_name

() : string

+

get_parent

() : Component

+

get_hier_name

() : string

+run()

Stimuli_Component

+gen :

HiLevel_Generator

+

hit_gen

:

Hit_Generator

+

hit_drv_ar

:

Hit_Driver

array

+

trig_drv

:

Trigger_Driver

+

hit_mon_ar

:

Hit_Monitor

array

+

trig_mon

:

Trigger_Monitor

+

hit_ch

: Channel

+

trig_ch

: Channel

Hit_drv_ch_ar

: Channel array

+

hit_analysis_ar

: Channel array

+

trig_analysis

: Channel

+new(

hit_hook

:

hit_intf

,

trig_hook

:

trig_intf

)

+body()

Readout_Component

+

mon

:

Readout_Monitor

+analysis : Channel

+new(

readout_hook

:

readout_intf

)

+body()

Flag_Component

+

mon

:

Flag_Monitor

+analysis : Channel

+new(

flag_hook

:

flag_intf

)

+body()

Conformity_Checker

+

hit_chan

: Channel array

+

trig_chan

: Channel

+

readout_chan

: Channel

+

flag_chan

: Channel

#expected[$] :

Readout_Trans

#

obj

: Objection

+new()

+body()

#

service_hit

()

#

service_readout

()

#

service_flags

()Slide9

Verification Environment – Components (2)

9

Pixel Phase 2 Electronics Meeting during TK Week – 27-08-2013

Stimuli_Component

First stage: generation of high level transactions (randomized or from external file)

High level transactions are fed to Trigger_Driver (generation of trigger signal)and to Hit_Generator and Hit_Driver’s (generation of hits on each pixel of the matrix)Readout_ComponentGeneration of readout transactions using pixel chip outputsFlag_Component

Generation of flag transactions using pixel chip flags (pixel busy and PR buffer full)

Conformity_Checker

Receives input hit information, trigger information, output data and diagnostic information (pixel chip flags)

Reference model in the checker predicts DUT output from input transactions

Predicted output and actual output are compared

Pixel chip flags are always monitored

Production of report messagesSlide10

Verification Environment – Reporting (1)

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Pixel Phase 2 Electronics Meeting during TK Week

– 27-08-2013

Conformity_Checker

has successfully found conformity between input and outputWARNING: Conformity_Checker has found discrepancy between input and outputERROR : Conformity_Checker has found out that the PR buffer is full

Conformity_Checker has found out that a pixel is busy and thus an input hit has been lostSlide11

Verification Environment – Reporting (2)

11

Pixel Phase 2 Electronics Meeting during TK Week

– 27-08-2013

Example of console outputSlide12

12

Further Developments

On the DUT: replication of pixel regions

PR columns

Future support for L1 trigger and ROI readout

On the verification environment:Improve monitoring of lost hitsAdd sources of uncertainty (delays, time walk,

…)Standardize into UVM for more solid base classes and highly customizable reporting features

Pixel Phase 2 Electronics Meeting during TK Week

– 27-08-2013