PDF-ArchShield Architectural Framework for Assisting DRAM Scaling by Tolerating High Error

Author : olivia-moreira | Published Date : 2014-12-26

Nair DaeHyun Kim Moinuddin K Qureshi School of Electrical and Computer Engineering Georgia Institute of Technology pnair6 dhkim moingatechedu ABSTRACT DRAM scaling

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ArchShield Architectural Framework for Assisting DRAM Scaling by Tolerating High Error: Transcript

Nair DaeHyun Kim Moinuddin K Qureshi School of Electrical and Computer Engineering Georgia Institute of Technology pnair6 dhkim moingatechedu ABSTRACT DRAM scaling has been the prime driver for increasing the cap ac ity of main memory system over th. : Architectural Framework for Assisting DRAM Scaling By Tolerating High Error-Rates. Prashant. Nair. Dae. -Hyun Kim . Moinuddin. K. . Qureshi. 1. DRAM: Basic building block for main memory for four decades. In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses. Vivek Seshadri. Thomas Mullins, . Amirali. . Boroumand. , Onur Mutlu, . Phillip B. . Gibbons, Michael A. Kozuch, . Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. : Architectural Framework for Assisting DRAM Scaling By Tolerating High Error-Rates. Prashant. Nair. Dae. -Hyun Kim . Moinuddin. K. . Qureshi. 1. DRAM: Basic building block for main memory for four decades. DRAM Scaling. Prof. Onur Mutlu. http://www.ece.cmu.edu/~omutlu. onur@cmu.edu. HiPEAC. ACACES Summer School 2013. July 15-19, . 2013. The Main Memory System. Main memory is a critical component of all computing systems. 2014. 11/21/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. DRAM market entering a new phase – a more “normal” market – in 2015. by Exploiting the Variation in Local . Bitlines. . Jeremie S. Kim. . Minesh. Patel . Hasan Hassan . Onur. . Mutlu. . Motivation. : DRAM latency is a . major performance bottleneck. Problem. 2014. 9/30/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. Strange situation: demand is weakening while supply remains tight. Weakening PC-DRAM demand and supply mix issues in 2H14. Vinson Young. Prashant Nair. Moinuddin Qureshi. 1. MOORE’s LAW HITS BANDWIDTH WALL. 2. Moore’s scaling encounters Bandwidth Wall. 3D-DRAM MITIGATES BANDWIDTH WALL. 3. 3D-DRAM. Hybrid Memory Cube (HMC) from Micron, . Xiangyao. Yu. 1. , Christopher Hughes. 2. , . Nadathur. Satish. 2. , . Onur. Mutlu. 3. , Srinivas . Devadas. 1. 1. MIT . 2 . Intel Labs . 3. ETH Zürich. Motivation. In-package DRAM has . Unclonable. Functions . by Exploiting the Latency-Reliability Tradeoff . in Modern Commodity DRAM Devices. Jeremie. S. Kim. . Minesh. Patel . Hasan Hassan . . Onur. . Mutlu. . Motivation. Vivek Seshadri. Thomas Mullins, . Amirali. . Boroumand. , Onur Mutlu, . Phillip B. . Gibbons, Michael A. Kozuch, . Todd C. Mowry. Executive summary. Problem: Non-unit . strided. accesses. Present in many applications. Byzantine Architecture . Objectives. Outline the background affecting the period.. Isolate elements associated with Byzantine architecture.. Identify famous Byzantine buildings.. Recognize key terms from Byzantine architecture..

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