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EDMS 1283934 Outline 2 Motivation and overview EDMS 1283934 Outline 2 Motivation and overview

EDMS 1283934 Outline 2 Motivation and overview - PowerPoint Presentation

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EDMS 1283934 Outline 2 Motivation and overview - PPT Presentation

Discharge Loop Interface Box in detail First prototype Second prototype Profinet 11 Outline 3 11 Motivation and overview Discharge Loop Interface Box in detail First prototype Second ID: 801565

schmidt optocoupler loop trigger optocoupler schmidt trigger loop user profinet interface 2oo3 logic dlib test monitoring discharge tvs users

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Presentation Transcript

Slide1

EDMS 1283934

Slide2

Outline

2

Motivation and overview

Discharge Loop Interface Box in detailFirst prototypeSecond prototypeProfinet

[11]

Slide3

Outline

3

[11]

Motivation and overviewDischarge Loop Interface Box in detailFirst prototype

Second

prototype

Profinet

Slide4

Motivation

4

[11]

Protection system:Monitoring + ActuatorsIf Monitoring detects a fault:Actuators switch off system

1 single link is not

reliable enough.

2 redundant links provide

required safety

ITER Magnets offer a

different challenge

:

Maximize availability

Minimize fast dischargesTherefore, study of other architectures (2oo2,1oo3, 2oo3, etc).

M

M

M

A

A

A

Slide5

CERN TE-MPE-EP Jonathan Búrdalo jburdalo@cern.ch

5

INTERFACE 11

INTERFACE2..10

INTERFACE1

PROFIBUS

DP / PROFISAFE

IM 153-2H

IM 153-2H

SYNCHRO. LINK

SM

326F 10FDO

2xPS per

CPU

2x PS Periphery (SITOP)

2x CPU

414HF

2x Comm. Proc.

2x Profibus networks

Step7 + AWL + CFC +S7 F SW

ET200M

SM 326F

24DI

SM

336FAI 6FAI

SM

322 DO 8RO

IM 153-2H

IM 153-2H

SM

326F 10FDO

ET200M

SM 326F

24DI

SM

336FAI 6FAI

SM

322 DO 8RO

SM

323

8 DIDO

IM 153-2H

IM 153-2H

SM

326F 10FDO

SM 326F

24DI

SM

336FAI 6FAI

SM

322 DO 8RO

SM

331

8 AI

QD

FDU 1..9

PC

QD

FDU 1..9

PC

QD

FDU 1..9

PC

SAME 11 INTERFACES FOR DIFFERENT USERS

Slide6

Outline

6

Motivation and

overviewDischarge Loop Interface Box in detailFirst prototypeSecond prototype

Profinet

[11]

Slide7

DLIB: Purpose

7

[11]

Roles: Simple interface for user signals with the 2oo3 discharge loops.Transmit fast discharge requests to different users.Galvanic Isolation between Users and PLC.

Unique way of

dealing with client diversity

(

ie

. different interlocks systems, electronics, voltages…).

Independent of upgrades at the user side.

Responds to required

dependability

and provides safe and reliable interlocking in both directions.Simplified test and commissioning (common diagnostics and monitoring).Remote test facility as from the level of the client connection.

Slide8

DLIB: General Diagram

8

[11]

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

Slide9

DLIB: How

does it work?

9

[11]

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

Slide10

DLIB: from USERS to Interface

10

Users send status

through 3

independent

Current Loops.

Current limited

by the interface box (fixed current source).

Design used at

CERN with success

(more than 220 similar interface boxes in use).

2oo3 Logic opens

discharge loop.

Slide11

DLIB: General Diagram

11

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

TVS

TVS

Slide12

DLIB: from Interface to USERS

12

Transmit to user the status

of the discharge loop links.

1 to 1

because of dependability requirements.

Users

MUST

make the 2oo3 evaluation of the signals.

Optocoupler

acting as dry contact and

galvanic isolation

with the User

Slide13

DLIB

: General Diagram

13

[11]

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

TVS

TVS

Slide14

DLIB: Test and Monitoring

14

[11]

The Prototype V1

Interfaces

had

a Profibus

slave

.

V2 uses PROFINET with a new

ASIC

called

TPS-1

.

16 bits of data

in each direction.

Status

of discharge loop, clients

and extra info

(temp, use of 2oo3 logic, configuration…).

Managed by

FPGA,

Actel

ProASIC3

.

Due to time stamping limitations of this solution, and the availability of a new chip,

Prototype V2 uses a ITER compliant solution based on Profinet

(Industrial Ethernet based Fieldbus).

Slide15

DLIB: General Diagram

15

[11]

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

TVS

TVS

Slide16

DLIB: Connectors

16

[11]

Use

compact

and

fully enclosed

mechanics.

BURNDY connectors offer

good EMC and dependability

.

8 and 12 pins, male and female, to

avoid misconnections

.

Diagnostics

port

in front panel for

monitoring

with Profinet

.

Slide17

Outline

17

Motivation and overview

Discharge Loop Interface Box in detailFirst prototypeSecond prototypeProfinet

[11]

Slide18

Experience from first Prototype

18

[11]

The first prototype was

assembled

and

tested thoroughly

.

Small test board with switches and LEDs to simulate the discharge loop and the users (at 24 V and 5 V).

Everything “analogue” works

according to specifications.

Profibus link has been tested successfully as well.

Integration and tests with PLC

were done by M. Zaera in Valencia.

A

first version is installed at ITER

since October for the HTS current leads tests. This will serve as a real test of the devices and

architecture

.

PLC + 2

DL

I

nterface

Boxes

configured with 1oo2 Logic.

It “survived” a

Preliminary Design Review

at ITER.

Slide19

Outline

19

Motivation and overview

Discharge Loop Interface Box in detailFirst prototypeSecond prototypeProfinet

[11]

Slide20

Second

Prototype20

Design is finished and we manufactured 5 units that are working and ready for use. The analogue part and interfaces with discharge loop and clients remain mainly unchanged except for small tweaks.

The functionality

it’s the same.

It

can work

together with a first prototype.

Main difference is the use of

Profinet

instead of Profibus for monitoring. A brand new chip,

TPS-1 from

Renesas is used to manage the Profinet stack.

As it’s Ethernet based: substitution of the frontal DB-9 connector for 2 RJ-45 ports.

Allows precise

time stamping of 1ms or less.

(to be tested yet)

Much easier and faster to implement from the PLC point of view.

4

devices will be taken to ITER next week

and

sent to the different clients

for early testing of the interface.

Slide21

Outline

21

Motivation and overview

Discharge Loop Interface Box in detailFirst prototypeSecond prototypeProfinet

[11]

Slide22

Profinet

22

Profinet offers several advantages over Profibus:

Profibus DPProfinet IOTransmission Tech.RS485-likeInd.

Ethernet

Data Exchange

Only by request

Cyclical or request

Transfer

Rate

Max. 12 Mbit/s

100 Mbit/s

full duplex# of devices126 (and complicated)

Arbitrary

Other data (IT services)No

YesDevice description (gsd

)Keyword based

XML basedData priority

Same for every slaveConfigurableTopology

Star and tree

Line, tree, ring

Slide23

TPS-1

23

This

brand new chip is in charge of the Profinet stack.196 pins 1mm pitch BGA package + 2 Fast Ethernet ports.Documentation has been quite a

challenge

(missing information).

A lot of emails exchanged with support and several surprises.

Frist time programming

of the chip is tedious.

But then it

works incredibly well

.

Next Steps:Try the Isochronous Real Time mode (to achieve 1 ms

sync)

Test with a Siemens PLC and play around with this synchronization options.

Slide24

End

24

[11]

THANKS FOR YOUR ATTENTION!

Slide25

DLIB: Integration in D. Loop

25

The Interface is able to

read the status

of the Discharge loop but

also to OPEN

it.

PLC

generates current

of 10mA and 24V.

Worst case:

2 V drop per Interface Box:

Maximum of

12 Interface Boxes

per Loop with a 24 V PLC supply.

+24 V

10mA

GND

Slide26

DLIB: General

Diagram

26

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

TVS

TVS

Slide27

DLIB: General

Diagram

27

DL+ IN

DL+ OUT

DL- IN

DL- OUT

FROM_USER +/-

TO_USER +/-

OPTOCOUPLER

OPTOCOUPLER

TRIGGER SCHMIDT

OPTOCOUPLER

2oo3 LOGIC

LOOP BREAKER

(Optocoupler)

TRIGGER

SCHMIDT

TRIGGER SCHMIDT

TRIGGER SCHMIDT

FPGA

(Test & Monitoring)

PROFINET

TestControl

TestPattern

RELAY

TVS

TVS

Slide28

DLIB: 2oo3 Logic

28

The 3 inputs from USERS are evaluated with

2oo3 logic

, keeping the loop closed, or open.

Inputs and outputs are

monitored

.

2oo3 should be the default configuration

, although exceptionally and justified, some clients can use 1oo2 logic (HW selector on board).

Logic Diagram: